SERVICE MANUAL
C= Commodore
Produced By:
Commodore International Spare Parts GmbH
Braunschweig, West Germany
SERVICE MANUAL
A500
OCTOBER, 1990 PN-314981-04
INTERNATIONAL EDITION
COMMODORE “INTERNATIONAL EDITION”? SERVICE MANUALS CON-
TAIN PART NUMBER INFORMATION WHICH MAY VARY ACCORDING TO
COUNTRY. SOME PARTS MAY NOT BE AVAILABLE IN ALL COUNTRIES.
Commodore Business Machines, Inc.
1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A.
Commodore makes no express or implied warranties with
regard to the information contained herein. The infor-
mation is made available solely on an as is basis, and the
entire risk as to completeness, reliability, and accuracy
is with the user. Commodore shall not be liable for any
damages in connection with the use of the information
contained herein. The listing of any available replacement
part herein does not constitute in any case a recommenda- _
tion, warranty or guaranty as to quality or suitability of
such replacement part. Reproduction or use without ex-
press permission, of editorial or pictorial content, in any
matter is prohibited.
This manual contains copyrighted and proprietary information. No part
of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical, photo-
copying, recording or otherwise, without the prior written permission
of Commodore Electronics Limited.
Copyright © 1990 by Commodore Electronics Limited.
All rights reserved. Printed in U.S.A.
SECTION 1
SPECIFICATIONS
A500 SERVICE MANUAL
Amiga A500 Specifications
Central Processor
Memory
Disks
Mouse
Interfaces
Supported Monitors
Power Requirements
Temperature Requirements
Humidity Requirements
Motorola MC68000
512K bytes RAM expandable to 1M
3-1/2 inch double-sided double-density microdisks
with 880K bytes formatted storage capacity per
disk
Mechanical, .13 mm/count (200 counts per inch)
RS-232 serial interface
Centronics®-compatible parallel interface
External disk interface
Mouse/Game controller interface
Additional game controller interface
Keyboard interface
Two audio outputs for stereo sound
Memory cartridge interface
Expansion interface
Analog RGB, digital RGB, monochrome (com--
posite video), and standard televisions
99 to 121 volts AC 54 to 66 Hz
For operation:
5 to 40 degrees Centigrade
(41 to 104 degrees Fahrenheit)
For storage:
-40 to 60 degrees Centigrade
(-40 to 140 degrees Fahrenheit)
20% to 90% relative humidity,
non-condensing
SECTION 2
THEORY OF OPERATIONS
A500 SERVICE MANUAL
Amiga 500 Memory Map
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Full 68000
Bus
Bi Directional
Tri State Latch
KEYBOARD
8520 CHIPS (2)
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32
DRAM
512K Std.
1MB optional
A500 Block Diagram
Printer Port
Disk Control
RS232 Control!
:
$2
Ports (2)
VIDEO HYBRID
TVANVW FDTAUS 00SV
A500 SERVICE MANUAL
Theory of Operation
The AMIGA computer is a high-performance system with advanced graphics and
audio features. The principal hardware features consist of the 68000 micro-
processor which runs at 7.2 MHz, 512K RAM, expandable to 1MB, and
configurable to 8MB, 2 parallel /O chips, one control chip (GARY) and 3
custom VLSI chips that provide the unique capabilities for animation, graphics
and sound.
68000 Microprocessor
The 68000 is the CPU of the system. All other resources are under software
control via control data issued from it. All 3 custom chips have control registers
that are written by the 68000.
The 68000 communicates with the rest of the computer via its address bus, data
bus and control lines. Notice that in the block diagram the 3 custom chips do not
reside directly on the 68000 buses. When the 68000 starts a bus cycle that is
intended for the custom chips or the display RAM, the bus control chip detects
whether or not the display RAM buses are available. The control chip will not
assert the acknowledge signal (/DTACK) back to the 68000 until the display
RAM buses are available. Once the 68000 receives /DTACK it completes the bus
cycle. Connecting the display RAM buses to the 68000 buses is discussed further
in the section on bus control. Because the display RAM is capable of approxi-
mately twice the bandwidth of the 68000, the 68000 is usually not delayed by
waiting for the display buses to become available.
The 68000 can fetch instructions from:
Display RAM
ROM
The 68000 can read and write data directly to:
Display RAM
Parallel /O Chips
3 Custom I.C.s
ROM
A500 SERVICE MANUAL
$0 S2 $4 SB SO S2 S4 Sw Sw Sw Sw Sw Sw Sw Sw Sw Sw S8 SO S2 S4 Sw Sw Sw Sw Sw Sw 88 80
CLK r UU
AS \ / \ / \ /
UDS \ / \ / \ /
LDS \ / \ / \ /
{Normal Cycle += - = - 68000 Peripheral Read Cycle = - - += 68000 Peripheral Write Cycle <4
SIGNAL SUMMARY
Signal Name
Address Bus
Data Bus
Address Strobe
Read/Write
Upper and Lower Data Strobes
Data Transfer Acknowledge
Bus Request
Bus Grant
Bus Grant Acknowledge
Interrupt Priority Level
Bus Error
Reset
Halt
Enable
Valid Memory Address
Valid Peripheral Address
Function Code Output
Clock
Power Input
Ground
*Open Drain
CPU Machine Cycle
Mnemonic
Al-A23
DO-D15
AS
R/W
UDS, LDS
DTACK
BR
BG
BGACK
IPLO, IPLI, IPL2Z
FCO, FC1, FC2
CLK
Vcc
GND
Input/Output
Output
Input/Output
Output
Output
Output
Input
Input
Output
Input
Input
Input
Input/Output
Input/Output
Output
Output
Input
Output
Input
Input
Input
AO is internal to 68000
Active State Three State
High Yes
High Yes
Low Yes
Read-High
Write-Low aS
Low Yes
Low No
Low No
Low No
Low No
Low No
Low No
Low No*
Low No*
High No
Low Yes
Low No
High Yes
High No
2-4
* A500 SERVICE MANUAL
The 68000 transmits data and control to and from the peripherals via the parallel
V/O and the 3 custom chips.
7M is the processor clock to the 68000. C1, C3 and CDAC are used to clock the
custom chips and determine the timing of signals to the memory arrays.
ROM
The ROM contains the kernel and DOS routines; it is 128K x 16.
Parallel I/O
The 2 multipurpose 8520 I/O chips provide the following:
I/O to and from the parallel port connector
Control lines to and from the joystick/mouse ports
A control line to the front panel LED
Internal control lines
Keyboard control lines, clock and data
Serial port control lines
Floppy disk interface control lines
Internal timers
These 2 chips reside on the 68000 buses and are read and written by the 68000.
Clocks Generator
The entire computer board is run synchronously to the 3.57954Mhz color clock
(C1). This is accomplished by generating a number of sub-multiple frequencies
from our master 28.63636Mhz crystal oscillator. The following are the primary
clocks on the board:
Name Description
Cl The 3.579545Mhz Color Clock
C2 Cl shifted 45 degrees later
C3 Cl shifted 90 degrees later
C4 C1 shifted 135 degrees later
7™M Cl XORed with C3* (7.15909Mhz)
DAC 7M shifted 90 degrees later
2-5
A500 SERVICE MANUAL
7M is the processor clock for the 68000 microprocessor. C1-C4 and DAC are
used to clock the custom chips and for determining the timing of signals to
the memory arrays.
The above frequencies are true for NTSC Amigas. A PAL Amiga will operate
slightly slower, with a main clock of 28.37516Mhz. This is divided down to
get 7M = 7.09379Mhz and Cl = 3.546895Mhz. A special circuit is required
to take five fourths of Cl to derive the PAL colorburst frequency of
4.43361875Mhz.
The following clocks are available at the edge connector:
Name Pin _ Description
C3* 14 C3 inverted
CDAC 15 DAC equivalent
Cl* 16 Cl inverted
Note that 7M (the processor clock) is not available at the connector; it can be
easily generated by:
C3* XNOR Cl1* = 7M equivalent
If you need a 14.31818Mhz synchronous clock, you can generate it by:
(7Mequiv) XOR (CDAC) = 14M equivalent
ibe, heel “he ole (ee ea
7M SyncdS2
— ~1391 ——~
Amiga System Clocks
2-6
A500 SERVICE MANUAL
The 3 Custom Chips
The 3 custom chips provide very fast manipulation of graphics and audio data in
the display RAM. All the major functions in the chips are DMA driven; that is,
streams of data are moved between the custom chips and display RAM under
DMA control. These streams of data are acted upon by the custom chips. Fat
Agnus, custom chip #1, contains 25 dedicated purpose DMA counters.
The 3 chips have control registers which are usually loaded by the 68000.
However, Fat Agnus also has the capability of loading control registers in the
other 2 custom chips. When Fat Agnus performs a bus cycle, it outputs a code on
the Register Address Bus telling the other 2 chips the nature of the bus cycle.
This is necessary because many of the bus cycles provide data to or from the
other 2 chips, thus they must cooperate appropriately.
In addition to manipulating data in the display RAM, the custom chips output
streams of data to the video output circuits and audio output circuits, and they
move data to and from the floppy disks and serial port.
Note that the display RAM buses can be completely isolated from the 68000
buses by Fat Agnus and Data Bus drivers. Thus, Fat Agnus can be performing a
bus cycle on the display buses simultaneously with the 68000 performing a bus
cycle on its buses. This parallelism increases throughout.
Bus Control, Address/Data MUX, Address Driver
The bus control logic resides in the control chip (GARY) and Fat Agnus. They
provide 3 major functions, they:
Synchronize the 68000 to the current phase of C1
Arbitrate between the 68000 and Fat Agnus for the display buses
Generate DRAM timing for the video RAM bus drivers appropriate to the
current cycle
Synchronizing the 68000 to C1 is straightforward, since the 68000 is clocked by
7M which is twice the frequency and synchronous to C1. If the 68000 starts a bus
cycle in the wrong phase of C1, the bus control chip merely delays /DTACK long
enough so that the 68000 will complete the bus cycle in the desired phase
relationship to C1. This phase relationship is necessary because the custom chips
and the display RAM are clocked by Cl.
2-7
A500 SERVICE MANUAL
Arbitration is very simple. Fat Agnus tells the bus control prior to taking the
display RAM buses by asserting an input to the control chip (GARY) called /
DBR. Whenever Fat Agnus has the display buses and the 68000 wants them, the
68000 is held off by not giving it /DTACK. In this state the 68000 has no effect
on the display buses until the bus controller enables the bus drivers.
Fat Agnus generates the DRAM timings and does all address multiplexing. If the
68000 is running a video memory cycle, its addresses are routed through Fat
Agnus onto the multiplexed address lines. If the custom chips are running a
memory cycle the addresses are routed to the multiplexed address lines from
internal address register.
Display RAM
The display RAM is a 512K read/write memory that resides on the RAM address
and RAM data buses. It is expandable to 1M bytes by the addition of the RAM
expansion module. It is implemented using standard 256K x 1 dynamic RAMs,
refreshed by Fat Agnus.
The display RAM is really used for much more than just holding graphics data. It
also stores code and data for the 68000.
Custom Control Chips
The Amiga’s animation, graphics and sound are produced by three custom chips.
Fat Agnus (8370), Denise (8362) and Paula (8364). A fourth custom chip, Gary
serves as the control chip. The following pages include pin diagrams, feature
lists, and block diagrams for these chips.
2-8
A500 SERVICE MANUAL
Custom Animation Chip
Features:
e Bit Blitter — Uses hardware to move display data
— Allows high speed animation — Frees the
CPU for other concurrent tasks
¢ Display Synchronized Coprocessor
© Controls 25 DMA Channels — Allows the disk
and sound to operate with minimal CPU inter-
vention
© Generates all system clocks from the 28 Mhz
oscillator
© Generates all control signals for the video RAM
and expansion RAM card
¢ Provides the address to the video and expansion
RAM multiplexing
Fat Agnus
Lette!
tt et mt mt mt Q->~ ~~ BE Orw
QQAG0QCKDAHNHYH
eaereeersrosiacea
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ge
? A} “sa i} s
airy thee Y sofas ‘a2 as aT) My tebe tet Yee
One Megabyte Agnus use in
Commodore A500 Computers.
Commodore Business Machines does not support the One Megabyte ad-
dressing feature of the Fat Agnus 8372 IC in A500 Computers.
Regardless of the version of Fat Agnus, all A500’s have been factory
jumper set to be functionally identical.
8370 Fat Agnus chips are used on rev 5 boards with 256K x 1 DRAMS.
8372 Fat Agnus chips are used on rev 6a boards with 256K x 4 DRAMS.
The boards are functionally interchangable. Each will support 512K of
chip RAM and 512K of expansion RAM with an A501 installed.
Enabling the One Megabyte feature, at the customers’ request, will void
the warranty. Instructions detailing implementation of the One Megabyte
addressing have been circulated without Official Approval and Com-
modore does not assume any liability for damages resulting from this
mode of operation in the A500.
2-9
OI-Z
AGA) -RGAB
Buffer
16) MUX Register Address Decoder
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Bs ° =
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5 a Sprite OMA
28.6363GMHZ Se a. Control Logic Audio Olsk ond
Ss |¢e OMA Refresh
Sprite Vertice) Contro) OMA
Position Conmpore Logic Control
Logic
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1
COAC « S ‘a ree s 2° ick ana
1a oO
Sync. Counters |Sprite Verticel oe ‘ otha
becaakie seetttene Fee ee Fen ieteks Recta lees
Registers Control 9
LIGHT PEN Registers
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OATA BUS ((16)
Register Address Decoder
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Fat Agnus Block Diagram
TVANVA AOIANAS 00SV
Features:
@ Many different resolutions
320 x 200 up to 640 x 400
© 4096 colors on a TV or RGB monitor
@ Eight re-usable sprite controllers
@ 60 or 80 column text
@ Same software for all TVs and monitors
Name
D0-D6
MI1H
MOH
RGAI-8
/BURST
Vcc
RO-3
BO-3
G0-3
N/C
/ZD
N/C
7M
CCK
Vss
MOV
M1V
D7-D15
A500 SERVICE MANUAL
Custom Graphics Chip
Denise
1
2
3
4
5
6
7
8
9
Description
Data Bus Lines 0-6
Mouse | Horizontal
Mouse 0 Horizontal
Register Address 1-8
Color Burst
+5 VDC
Video Red Bit 0-3
Video Blue Bit 0-3
Video Green Bit 0-3
No Connection —
Background Indicator
No Connection
7.15909 MHz Clock
Color Clock
Ground
Mouse 0 Vertical
Mouse | Vertical
Data Bus Lines 7-15
=) ° 5 COOOF OF HHS
i=
©
2-11
(4 4
Collision
Storage
Register
Collision
Detect
Logic
Bit Plane
Serial.
Collision Bit Plane Sprite
Control Data Registe Data
Register 6 Registers 16
Liteett=
Data Bus (16)
Register Address Decode
Denise Block Diagram
Sprite Position
Compare Logic
Horizontal
Sync.
Counter
Prioty [Y &
Control
Bit Plane
Priority
& Control
Registers
32
Color
Registers
Sprite
Horizontal
Position
Registers
| | | i
Burst
TVANVA ADIAUAS 00SV
A500 SERVICE MANUAL
Custom Sound/Peripherals Chip
Paula
Features:
© Four voices of sound output configured
as two stereo channels
@ Nine octaves
1
2
3
4
5
6
7
8
9
© Complex waveforms
@ Uses both amplitude and frequency modulation
© 1/O controls for disk data and controller ports
®@ Microdisk controller
© Interrupt control system
Pin Name Description Type
1-7 D2-D8 Data Bus Lines 2-8 VO
8 Vss Ground I
9,10 DO,D1 Data Bus Lines 0,1 VO
11 /RES System Reset I
12 DMAL DMA Request Line O
13-15 /IPLO-2 Interrupt Line 0-2 O
16-18 IINT2,3,6 Interrupt Level 2,3,6 I
19-26 RGAI1-8 Register Address 1-8 I
27 Vcc +5 VDC I
28 CCK Color Clock I
29 CCKQ Color Clock Delay I
30 AUDB Right Audio O
31 AUDA Left Audio O
32 POTOX Pot 0X VO
33 POTOY Pot OY YO
34 VSSANA Analog Ground pt
35 POTIX Pot 1X vO
36 POTLY Pot LY YO
37 /DKRD Disk Read Data It
38 /DKWD Disk Write Data O
39 DKWE Disk Write Enable O
40 TXD Serial Transmit Data O
41 RXD Serial Receive Data I
42-48 D9-15 Data Bus Lines 9-15 VO
2-13
vI-Z
’ Left Right
Audio Audio Disk UART POT
Output Output Out In In Out Ports
pat ree
to Agnus | DMA
Logic
eas Data | Pre Buffers
cor : Sep Comp Latches
abbas (Bi-Dir)
i Audio
Control
Counters
Control
Logic
Control
Counters
Control
Counters
Control
Logic
Int.
i egisters Registers egisters
to 68000 Logic 7 S 2
EXT.
interrupt
Inputs
DB
$8) Register Address Decode 8
Buffer
Timing Strobe Decodes
Buffer
Paula Block Diagram
TVANVW ADIANAS 00SV
A500 SERVICE MANUAL
Custom Control Chip
Gary
Features:
© Provides all bus control signals.
1
2
3
4
5
6
7
8
9
@ Provides all address decoding.
@ Generates the 68000 VPA signal.
@ Handles some of the floppy circuitry.
© Provides keyboard reset interface.
For signal descriptions see Schematic #312511 (sheet 1 of 9)
2-15
A500 SERVICE MANUAL
e
Gary Block Diagram
Address decode
68000
a ) ee RAM Enable (RAME)
Address Strobe (AS) RGA Enable (RGAE)
UDS, LDS ROM Enable (ROME)
Clocks 2 Real time clock read
(C2, C3) and write (RTCR, RTCW)
Override (OVR) VPA
Overlay (OVL)
Processor read write
(PRW)
Expansion Board
Present (EXPEN)
CDR Bidirectional
DBR CDW tri-state latch
control
Bus LATCH
XRDY Control
Override DTACK
(OVR) BLS
Floppy Control
Logic
Reset
KReset
Keyboard Reset
Halt
2-16
A500 SERVICE MANUAL
Complex Interface Adapter
1
2
3
4
5
6
7
8
9
10
INTERFACE SIGNALS
E Clock Input
Peripheral Clock from 68000 (10
cycles of 7.16Mhz clock — 6 high, 4
low)
CS — Chip Select Input
The CS input controls the activity of
the 8520. A low level on CS while 02
is high causes the device to respond
to signals on the R/W and address
(RS) lines. A high on CS prevents
these lines from controlling the 8520.
The CS line is normally activated (low)
at 02 by the appropriate address
combination.
R/W — Read/Write Input
The R/W signal is normally supplied
by the microprocessor and controls
the direction of data transfers of the
8520. A high on R/W indicates a read
(data transfer out of the 8520), while
a low indicates a write (data transfer
into the 8520).
RS3-RSO — Address Inputs
The address inputs select the inter-
nal registers as described by the
Register Map.
DB7-DB0 — Data Bus Inputs/
Outputs
The eight bit data bus transfers infor-
mation between the 8520 and the
system data bus. These pins are high
impedance inputs unless CS is low
and R/W and 02 are high, to read the
device. During this read, the data bus
output buffers are enabled, driving the
data from the selected register onto
the system data bus.
INT — (IRQ) Interrupt Request
Output
IRQ is an open drain output normally
connected to the processor interrupt
input. An external pullup resistor
holds the signal high, allowing multi-
ple IRQ-outputs to be connected
together. The IRQ output is normally
off (high impedance) and is activated
low as indicated in the functional
description.
RES — Reset Input
A low on the RES pin resets all inter-
nal registers. The port pins are set as
inputs and port registers to zero
(although a read of the ports will
return all highs because of passive
pullups). The timer control registers
are set to zero and the timer latches
to all ones. All other registers are
reset to zero.
2-17
REGISTER MAP
RS3
“a~a-v-t-s-]' =]! =| OC CCACACOO
RS2
~“~ +0000 -4% 4400 oo
RS1
oo-,-+-00-4% 40 o- 400
Ss
00-07
DATA BASE BUFFERS
CHIP ACCESS CONTROL
R/W 02 CS RS3 RS2 RS1 RSO RES
RSO REG
0 0 PRA
1 1 PRB
0 2 DDRA
1 3 DDRB
0 4 TA LO
1 5 TA HI
0 6 TB LO
1 7 TB Hl
0 8
1 9
0 A
1 B
0 C SDR
1 D ICR
0 E CRA
1 F CRB
A500 SERVICE MANUAL
PAO-PA7
D PC
Peripheral Data Reg. A
Peripheral Data Reg. B
Data Direction Reg. A
Data Direction Reg. B
Timer A Low Register
Timer A High Register
Timer B Low Register
Timer B High Register
Event LSB
Event 8-15
Event MSB
No Connect
Serial Data Register
Interrupt Control
Register
Control Register A
Control Register B
2-18
A500 SERVICE MANUAL
FUNCTION DESCRIPTION
I/O Ports (PRA, PRB, DDRA, DDRB)
Ports A and B each consist of an 8-bit Peripheral Data Register (PR) and an 8-bit Data Direc-
tion Register (DDR). If a bit in the DDR is set to the corresponding bit in the PR it is an
output. If a DDR bit is set to zero, the corresponding PR bit is defined an an input. On a
READ, the PR reflects the information present on the actual port pins (PAO-PA7, PBO-PB7)
for both input and output bits. Port A has both passive and active pullup devices, providing
both CMOS and TTL compatibility. It can drive 2 TTL loads. Port B has only passive pullup
device and has a much higher current-sinking capability.
Handshaking
Handshaking on data transfers can be accomplished using the PC output pin and the FLAG
input pin. PC will go low on the 3rd cycle after a PORT B access. This signal can be used
to indicate ‘‘data ready” at PORT B or ‘‘data accepted” from PORT B. Handshaking on
a 16-bit data transfers (using both PORT A and PORT B) is possible by always reading or
writing PORT A first. FLAG is a negative edge sensitive input which can be used for receiv-
ing the PC output from another 8520 or as a general purpose interrupt input. Any negative
transition on FLAG will set the FLAG interrupt bit.
Reg Name D7 D6 D5 D4 D3 D2 D1 DO
PRA PA7 PA6 PAS PA4 PA3 PA2 PA1 PAO
PPB PB7 PB6 PBS PB4 PB3 PB2 PB1 PBO
DDRA DPA7 DPA6 ODPAS ODPA4 =ODPA3 ODPA2 ~~ ODPA1 DPAO
DDRB ODPB7 ODPB6 ODPBS ODPB4 OPB3 ODPB2 ~ ODPBI1 DPBO
on +~ &
Interval Timers (Timer A, Timer B)
Each interval timer consists of a 16-bit read-only Timer Counter and a 16-bit write-only Timer
Latch. Data written to the timer is latched in the Timer Latch, while data read from the timer
are the present contents of the Timer Counter. The timers can be used independently or
linked for extended operations. The various timer modes allow generation of long time delays,
variable width pulses, pulse trains and variable frequency waveforms. Utilizing the CNT
input, the timers can count external pulses or measure frequency, pulse width and delay
times of external signals. Each timer has an associated control register, providing indepen-
dent control of the following functions.
Start/Stop
A control bit allows the timer to be started or stopped by the microprocessor at any time.
PB On/Off
A control bit allows the timer output to appear on a PORT B output line (PB6 for TIMER
A and PB7 for TIMER B). This function overrides the DDRB control bit and forces the ap-
propriate PB line to an output.
Toggle/Pulse
A control bit selects the output applied to PORT B. On every timer underflow the output
can either toggle or generate a single positive pulse of one cycle duration. The toggle out-
put is set high whenever the timer is started and is set low by RES.
2-19
A500 SERVICE MANUAL
One-Shot/Continuous
A control bit selects either timer mode. In one-shot mode, the timer will count down form
the latched value to zero, generate an interrupt, reload the latched value, then stop. In con-
tinuous mode, the timer will count from the latched value to zero, generate an interrupt,
reload the latched value and repeat the procedure continuously. In one-shot mode: a write
to Timer High (registers 5 for TIMER A, 7 for TIMER B) will transfer the timer latch to the
counter and inititate counting regardless of the start bit.
Force Load
A strobe bit allows the timer latch to be loaded into the timer counter at any time, whether
the timer is running or not.
Input Mode
Control bits allow selection of the clock used to decrement the timer. TIMER A can count
02 pulses or external pulses applied to the CNT pin. TIMER B can count 02 pulses, exter-
nal CNT pulses, TIMER A underflow pulses or TIMER A underflow pulses while the CNT
pin is held high.
The timer latch is loaded into the timer on any timer underflow, on a force load or following
a write to the high byte of the prescaler while the timer is stopped. If the timer is running,
a write to the high byte will load the timer latch, but not reload the counter.
READ (TIMER)
REG Name
4 TALO TAL7 TAL6 TALS TAL4 TAL3 TAL2 TAL1 TALO
5 TAHI TAH7 TAH6 TAHS TAH4 TAH3 TAH2 TAH1 TAHO
6 TBLO- TBL7 TBL6 TBL5 TBL4 TBL3 TBL2 TBL1 TBLO
7 TB HI TBH7 =TBH6 TBHS TBH4 TBH3 TBH2~~ TBH1 TBHO
WRITE (PRESCALER)
REG Name
4 TALO- PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PALO
5 TA HI PAH7 PAH6 PAHS5 PAH4 PAHS PAH2 PAH1 PAHO
6 TBLO- PBL7 PBL6 PBL5 PBL4 PBL3 PBL2 PBL1 PBLO
7 TB HI PBH7 PBH6 PBH5 PBH4 PBH3 PBH2 PBH1 PBHO
TOD (TICK)
TOD consists of a 24 bit binary counter. Positive edge transitions on this pin cause the binary
counter to increment. The TOD pin has a passive pull-up on it. A programmable ALARM
is provide for generating an interrupt at a desired time. The ALARM registers are located
at the same addresses as the corresponding TOD register. Access to the ALARM is governed
by a Control Register bit. The ALARM is write-only; any read of a TOD address will read
time regardless of the state of the ALARM access bit
2-20
A500 SERVICE MANUAL
A specific sequence of events must be followed for proper setting and reading of TOD. TOD
is automatically stopped whenever a write to the register occurs. The clock will not start
again until after a write to the LSB Event Register. This assures TOD will always start at
the desired time. Since a carry from one stage to the next can occur at any time with respect
to a read operation, a latching function is include to keep all Time of Day information cons-
tant during a read sequence. All TOD registers latch on a read of MSB event and remain
latched until after a read of LSB Event. The TOD clock continues to count when the output
registers are latched. If only one register is to be read, there is no carry problem and the
register can be read ‘‘on the fly’, provided that any read of MSB Event is followed by a
read of LSB Event to disable the latching.
READ
REG Name
8 LSB Event E7 E6 E5 E4 E3 E2 E1 EO
9 Event 8-15 E15 E14 E13 E12 E11 E10 E9 E8
A MSB Event E23 E22 E21 E20 E19 E18 E17 E16
WRITE
CRB7=0
CRB7=1 ALARM
(SAME FORMAT AS READ)
Serial Port (SDR)
The serial port is a buffered, 8-bit synchronous shift register system. A control bit selects
input or output mode. In input mode, data on the SP pin is shifted into the shift register
on the rising edge of the signal applied to the CNT pin. After 8 CNT pulses, the data in
the shift register is dumped into the Serial Data Register and an interrupt is generated. In
the output mode, TIMER A is used for the baud rate generator. Data is shifted out on the
SP pin at 1/2 the underflow rate of TIMER A. The maximum baud rate possible is 02 divided
by 6, but the maximum useable baud rate will be determined by line loading and the speed
at which the receiver responds to input data. Transmission will start following a write to
the Serial Data Register (provided TIMER A is running and in continuous mode). The clock
signal derived from TIMER A appears as an output on the CNT pin. The data in the Serial
Data Register will be loaded into the shfit register then shift out to the SP pin when a CNT
pulse occurs. Data shifted out becomes valid on the falling edge of CNT and remains valid
until the next falling edge. After 8 CNT pulses, an interrupt is generated to indicate more
data can be sent. If the Serial Data Register was loaded with new information prior to this
interrupt, the new data will automatically be loaded into the shift register and transmission
will be continuous. If no further data is to be transmitted, after the 8th CNT pulse, CNT
will return high and SP will remain at the level of the last data bit transmitted. SDR data
is shifted out MSB first and serial input data should also appear in this format.
The bidirectional capability of the Serial Port and CNT clock allows several devices to be
connected to a common serial communication bus on which one acts as a master, sourcing
data and shift clock, while all other chips act as slaves. Both CNT and SP outputs are open
drain, with passive pull-ups, to allow such a common bus. Protocol for slave/master selec-
tion can be transmitted over the serial bus, or via dedicated handshaking lines.
REG Name
Cc SDR S7 S6 S5 S4 $3 S2 S1 So
2-21
A500 SERVICE MANUAL
Interrupt Control (ICR)
There are five sources of interrupts on the 8520: underflow from TIMER A, underflow from
TIMER B, TOD ALARM, Serial Port full/empty and FLAG. A single register provides mask-
ing and interrupt information. The Interrupt Control Register consists of a write-only MASK
register and a read-only DATA register. Any interrupt which is enabled by the MASK register
will set the IR bit (MSB) of the DATA register and bring the IRQ pin low. In a multi-chip
system, the IR bit can be polled to detect which chip has generated an interrupt request.
The interrupt DATA register is cleared and the IRQ line returns high following a read of
the DATA register. Since each interrupt sets an interrupt bit regardless of the MASK, and
each interrupt bit can be selectively masked to prevent the generation of a processor inter-
rupt, it is possible to intermix polled interrupts with true interrupts. However, polling the
IR bit will cause the DATA register to clear, therefore, it is up to the user to preserve the
information contained in the DATA register if any polled interrupts were present.
The MASK register provides convenient control of individual mask bits. When writing to
the MASK register, if bit 7 (SET/CLEAR) of the data written is a ZERO, any mask bit written
with a one will be cleared, while those mask bits written with a zero will be unaffected. If
bit 7 of the data written is a ONE, any mask bit written with a one will be set, while those
mask bits written with a zero will be unaffected. In order for an interrupt flag to set IR and
generate an Interrupt Request, corresponding MASK bit must be set.
READ (INT DATA)
REG Name
D IRC IR 0 0 FLG SP ALRM TB TA
WRITE (INT MASK)
REG Name
D IRC S/C x X FLG SP ALRM T TA
Control Registers
There are two control registers in the 8520: CRA and CRB. CRA is associated with TIMER
A and CRB is associated with TIMER B.
CRA:
BIT NAME FUNCTION
0 START 1=START TIMER A, 0=STOP TIMER A. This bit is automatically reset when
underflow occurs during one-shot mode.
1 PBON 1=TIMER A output appears on PB6, 0=PB6 normal operation.
2 OUTMODE 1=TOGGLE, 0=PULSE
3 RUNMODE 1=ONE-SHOT, 0 =CONTINUOUS
4 LOAD 1=FORCE LOAD (this is a STROBE input, there is no data storage, bit 4 will always
read back a zero and writing a zero has no effect.
5 INMODE 1=TIMER A counts positive CNT transitions, 0= TIMER A counts 02 pulses.
6 SPMODE 1=SERIAL PORT output (CNT sources shift clock). 0= SERIAL PORT input (ex-
ternal shift clock required).
7 TODIN 1=50 Hz clock required on TOD pin for accurate time.
0=60 Hz clock required on TOD pin for accurate time.
2-22
A500 SERVICE MANUAL
CRB:
BIT NAME FUNCTION
(Bits CRBO-CRB4 are identical to CRAO-CRA4 for TIMER B with the exception
that bit 1 controls the output of TIMER B on PB7).
5.6 INMODE Bits CRB5 and CRB6 select one of four input modes for TIMER B as:
CRB6 CRB5
0 0 TIMER B counts 02 pulses.
0 1 TIMER B counts positive CNT transitions.
1 0 TIMER B counts TIMER A underflow pulses.
1 1 TIMER B counts TIMER A underflow pulses while
CNT is high.
7 ALARM 1 =writing to TOD registers set ALARM, 0=writing to TOD registers sets TOD clock.
ELECTRICAL PARAMETERS
Absolute Maximum Ratings
Stresses above those listed may cause permanent damage to the circuit. Functional operation of
the device at these or any conditions other than those indicated in the operating conditions of the
specification is not implied. Exposure to the maximum ratings for extended periods may adversely
affect device reliability.
Supply Voltage Vcc -0.3V to 7.0V Operating Temp. Top 0°C to 70°C
Input/Output Voltage Vin -0.3V to 7.0V Storage Temp. Tstg -—55°C to 150°C
*All inputs contain protection circuitry to prevent damage due to high static discharges. Care should
be exercised to prevent unnecessary application of voltages in excess of the allowable limits.
ELECTRICAL CHARACTERISTICS (VCC +/- 5%, VSS = Ov, TA = 0.70 C)
CHARACTERISTICS SYMBOL MIN. TYP. MAX. UNIT
Input High Voltage Vih +2.4 _ Vec V
Input Low Voltage Vil -3.0 _- +0.8 Vv
Input leakage current lin — 1.0 2.5 pA
VIN=VSS + 5V (TOD, RW,
02, RES, RSO-RS3, CS)
PAO-7, PBO-7, TOD, Rpi 3.1 5.0 — Ko
FLAG, SP, CNT
Output leakage current for Itsi — +1.0 +10.0 pA
High Impedance State
VIN =4V to 2.4V (DB0-DB7, IRQ)
Output High Voltage Voh +2.4 _ Vec Vv
VCC =MIN, LOAD < —200pA
(PAO-PA7, DB0-DB7)
Output Low Voltage Vol — _ +0.40 V
(PAO-PA7, DB0-DB7)
VCC =MIN, LOAD<3.2pA
Output High Current (sourcing) loh ~ 200 - 1000 _ pA
VOH>2.4V (PAO-PA7, DBO-DB7)
Output Low Current (sinking) lol 3.2 — _ pA
VOL <.4V (PAO-PA7, DB0O-DB7)
Output Low Current (sinking) lol 13.0 — _- pA
VOL<.4V (PC, PBO-PB7)
Input Capacitance Cin _ 7 10 pf
Output Capacitance Cout — 7 10 pf
Power Supply Current Icc — 70 100 pA
2-23
A500 SERVICE MANUAL
TIMING DIAGRAMS
WRITE TIMING DIAGRAM
TR— --——-THW------ -—TF
------ TW — —-—-— —-—
02 INPUT
-~------ To-—-——-—
series aera
DATA OUT
-—-—-— Twes — — —- —
cs
monn XP | ——Ssr—SiS
RW TRWH — —
a < eee RE)
DB7-DB8
--- ws -—-
READ TIMING DIAGRAM
02 INPUT
ns. Ci
---TACC—— — —TOR-
2-24
2.2 Timing Characteristics
A500 SERVICE MANUAL
1MHZ
SYMBOL CHARACTERISTIC MIN MAX
02 CLOCK
TCYC Cycle Time 1000 10,000
TR, TF Rise and Fall Time = 25
TCHW Clock Pulse Width (High) 440 5,000
TCLW Clock Pulse Width (Low) 440 5,000
WRITE CYCLE
TPD Output Delay From 02 = 960
TWCS CS low while 02 high 280 aa
TADS Address setup time 58 =
TADH Address hold time 10 =
TRWS R/W setup time 58 =
TRWH RI/W hold time 10 _
TDS Data bus setup time 200 ae
TDH Data bus hold time 15 =
READ CYCLE
TPS Port setup time 300 a
TWCS(2) CS low while 02 high 280 =
TADS Address setup time 58 os
TADH Address hold time 10 =
TRWS R/W setup time 58 —
TRWH RW hold time 10 =
TACC Data access from RS3-RSO — 300
TCO(3) Data access from CS — 240
TDR Data release time 50 —
“See diagram on page 23 for timing relationships.
*NOTES:
1. All timings are referenced from VIL max and VIH min on inputs and VOL max and VOH min
on outputs.
2. TWCS is measured from the later of 02 high or CS low. CS must be low at least until the end
of 02 high.
3. TCO is measured from the later of 02 high or CS low. Valid data is available only after the
later of TACC of TCO.
2-25
SECTION 3
TROUBLESHOOTING
A500 SERVICE MANUAL
A500/A2000 SYSTEM TEST
System Test is an auto-boot diskette. Once booted its own cli window will open. Type the commands listed below
in order to run each test.
KEYTEST
SCREENTEST
SHOW.HIRES.TEST
SHOW BALLOON
CUBEROTE
SYSTEST
¢ Full keyboard test
e press all keys to confirm proper operation
click left mouse button in upper left corner to EXIT
e Keyboard matrix test
e pressing the keys indicated by the program will test the matrix and seven dedicated key
functions
¢ Screentest is low resolution graphic screen made up of 6 bit planes. Used to test RGB linearity
and HALF BRIGHTS.
@ screentest will display a RGB COLOR BAR scale and a 16 level gray scale in both normal
and half bright mode. Normal scales are on top.
e Press space bar to EXIT screen.
© Hires.Test is a 4 bit plane high resolution 640 by 400 screen that displays NTSC color bars,
8 level gray scales, horizontal resolution lines, and an interlace test.
© Press space bar to EXIT screen.
© Balloon is a 6 bit plane hold and modify picture used to verify proper HAM decoding.
¢ This will test for a bad Agnus or Denise chip.
¢ Press space bar to EXIT screen.
¢ Cuberote is an animated cube whose speed and direction is controlled by the mouse X-Y
position. The cube is blue with shading of three visible sides. Cuberote uses double buffer-
ing for a smooth animation. Direct manipulation of the Copper List permits the display
of 16 shades blue while only using 2 bit planes.
© Click left mouse button in upper left corner to EXIT screen.
Systest will run the following test Realtime clock, Blit, Chip/Fast Ram Sprites/Bliter, and
Disk 1/0.
¢ Reboot computer to EXIT program.
Type the following for customizing systest.
SYSTEST 246d ; A500 NO A501 PCB
SYSTEST 2436cd ; A500 WITH A501 OR A2000 PCB
SYSTEST 1245679d ; A500 NO A501 BURN-IN
SYSTEST 12345679cd ; A500 WITH A501 OR A2000 BURN-IN
SYSTEST 12345678d ; A500 NO A501 AGING
SYSTEST 12345678cd ; AS00 WITH A501 OR A2000 AGING
3-1
A500 SERVICE MANUAL
A500/A2000 SYSTEM TEST (Continued)
The system test may also be customized. Type the word SYSTEST then select any of the numeric alpha characters
listed below.
1 _LOOP Enable endless loop. This will test the real time clock and the blit only once.
Then cycle through any of the selected test.
2 _BLIT This will run BOXER as a background task for loading.
3 _EXTERNAL (FAST) RAM This will test ram at $C00,000 and $200,000 to $9FF,FFF if found. If Fast
ram is not detected program will pass but say FAST RAM NOT FOUND.
4 _EXTERNAL (CHIP) RAM This is the same as FAST RAM test except that it test from $0 to $800,000.
5 _EXTENDED RAM TEST This is an expanded version of Fast Ram. Along with unique address and
refresh various bit patterns are used. These are All Zeros, All Ones, All A’s
and All 5’s.
6 _DISK In order to test the disk I/O. Tracks 2 and 8 will first be formatted. Upon
successes $6DB6 will be written and verified from tracks 2 and 8.
7 _EXTENDED DISK For Extended Disk all ONES, ALL ZEROS, $AAAA and $5555 are used.
8 _EXTRA DISK SEEK During PCB and Burn-in testing this will seek only at a minimum. However
during Aging test it will use maximum seeking.
9 _DISK CYCLE This will test disk every 8 cycles if Loop test is also selected.
a _NO AUDIO Disable Audio test.
b _NO SPRITES Disable Sprite test.
c _CLOCK CHIP This will test the real time clock chip.
d _DISPLAY GRAPHICS CLOCK _ Displaying the graphics clock will test bliter indicating a bad agnus chip if
display is corrupt.
f _BLITER LINE DRAW This will test for extraneous bit set. Previously visual inspection of the
graphics clock was used to test bliter. However now the line draw feature
of agnus is tested through the program.
AMIGA 1.3 STARTUP SEQUENCE — OVERVIEW
1 - DELAY 1/3 SECOND (LET HARDWARE SETTLE)
2 - JUMP TO ROM CODE IN DIAG CART (IF FOUND)
3 - DISABLE/CLEAR ALL INTERRUPTS & DMA’S
4- TURN ON SCREEN
5 - DISPLAY DARK GREY SCREEN — HARDWARE OK
6 - CHECKSUM ROM — IF BAD DISPLAY RED SCREEN
7 - SET UP TEMPORARY EXCEPTION PROCESSING — IF SPURIOUS EXCEPTION OCCUR, DISPLAY
YELLOW SCREEN
8 - CONFIGURE LOCAL MEMORY (CHECK BOUNDARIES, SIZE) IF PROBLEM, DISPLAY GREEN SCREEN
9 - CHECK SOME CUSTOM IC REGISTERS — IF FAILURE, DISPLAY BLUE SCREEN
10 - RESTORE SCREEN — CHANGE TO LIGHT GREY = SOFTWARE OK
3-2
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING
SECTION 1 — BASIC PRELIMINARY CHECKS
There are a few basic checks which must be made on the A500 when troubleshooting a SYSTEM THAT DISPLAYS
NO VIDEO ON POWER UP IN ANY AVAILABLE VIDEO MODE. There are several things which may cause this
symptom but these BASIC SIGNALS MUST BE PRESENT in order for the system to operate. If all these Basic Checks
seem correct, more Advanced Checks are covered in SECTIONS 2 THRU 3.
All signals must be taken with power applied to the system unless specified.
A (P) preceding the step number indicates signals which must be measured as power is applied to the system.
ALL MEASUREMENTS ARE WITHIN A +10% TOLERANCE
ALL READINGS MUST BE TAKEN WITH AN OSCILLOSCOPE
(P) INDICATES SIGNALS WHICH MUST BE MEASURED ON SYSTEM POWER UP
STEP 1 Measure the voltage on pin | (right pin) on connector CN12
¢ Result = +5 VDC Level Continue to Step 2
STEP 2 Measure the voltage on pin 4 (left pin) on connector CN12
¢ Result = +12 VDC Level Continue to Step 3
STEP 3. Measure the voltage on pin 1 of IC U38 (MC1488)
e Result = —12 VDC Level Continue to Step 4
If any result is incorrect, Refer to Section 1.1 TROUBLESHOOTING THE A500 SYSTEM POWER SUPPLY
(P) STEP 4 Measure the signal on pin 41 (RST)* of IC US (GARY)
© Result = 0 to +5 VDC shortly after system power up Continue to Step 5
(P) STEP S5_ Measure the signal on pin 11 (RESET)* of IC U37 (74LS32)
¢ Result = 0 to +5 VDC shortly after system power up Continue to Step 6
(P) STEP 6 Measure the signal on pin 8 (IORESET)* of IC U37 (74LS32)
¢ Result = 0 to +5 VDC shortly after system power up Continue to Step 7
If any result is incorrect, Refer to Section 1.2 TROUBLESHOOTING THE A500 SYSTEM RESET
STEP 7 Measure the signal on pin 15 (CLK) of IC U1 (68000)
¢ Result = 7 MHZ Clock Continue to Step 8
STEP 8 Measure the signal on pin 4 (CCK)* of IC U33 (74F04)
e Result = Approximately 3.58 MHZ Clock Continue to Step 9
STEP 9 Measure the signal on pin 6 (CCKQ)* of IC U33 (74F04)
¢ Result = Approximately 3.58 MHZ Clock Continue to Step 10
STEP 10 Measure the signal on pin 10 (CDAC) of IC U33 (74F04)
© Result = Approximately 7 MHZ Clock Continue to Section 2
If any result is incorrect, Refer to Section 1.3 TROUBLESHOOTING THE A500 SYSTEM CLOCKS
ALL THE SIGNALS LISTED, STEP 1 THROUGH STEP 10, MUST BE PRESENT
FOR THE SYSTEM TO PRODUCE THE CORRECT VIDEO DISPLAY
IF ALL SIGNALS SEEM TO BE CORRECT, BEGIN THE STEPS LISTED IN
SECTIONS 2 THROUGH 3 — TROUBLESHOOTING THE A500 CONTROL SIGNALS
*INDICATES ACTIVE LOW
3-3
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 1.1 — TROUBLESHOOTING THE A500 SYSTEM POWER SUPPLY
By referring to this section, it is assumed that one or more of the +5 VDC, +12 VDC or — 12 VDC measurements
from BASIC PRELIMINARY CHECKS, STEPS | through 3 are incorrect.
LINE FILTER (LF1) PINOUTS — FROM FRONT OF PCB
Pin 4
*
+12V
+12V
*
Pin 5
Pin 3 Pin 2 Pin 1
* * *
+12V -—5V GND
-—12V VCC SH/GND
* * *
Pin 6 Pin 7 Pin 8
1.1.1 INCORRECT (+5) VDC SUPPLY
STEP 1
STEP 2
STEP 3
A500 SERVICE MANUAL
Disconnect the disk drive assembly and measure the voltage on pin | (right pin) of connector CN12
e Result = +5 VDC Level
e Result = Incorrect
Measure the voltage on pin 7 (VCC) of line filter (LF1)
e Result = +5 VDC Level
¢ Result = Incorrect
Measure the voltage on pin 2 (+5) of line filter (LF1)
e Result = +5 VDC Level
e Result = Incorrect
1.1.2 INCORRECT (+ 12) VDC SUPPLY
STEP 4
STEP 5
STEP 6
Defective Drive Assembly
Continue to Step 2
No +5 VDC Problem or
Open +5 VDC Trace
Continue to Step 3
Defective Filter LF]
Defective Power Supply or
Shorted Component
Disconnect the disk drive assembly and measure the voltage on pin 4 (left pin) of connector CN12
e Result = +12 VDC Level
e Result = Incorrect
Measure the voltage on pin 5 (+ 12V) of line filter (LF1)
¢ Result = +12 VDC Level
© Result = Incorrect
Measure the voltage on pin 4 (+ 12) of line filter (LF1)
¢ Result = +12 VDC Level
¢ Result = Incorrect
1.1.3 INCORRECT (- 12) VDC SUPPLY
STEP 7
STEP 8
Measure the voltage on pin 6 (—12V) of line filter (LF1)
¢ Result = —12 VDC Level
© Result = Incorrect
Measure the voltage on pin 3 (— 12V) of line filter (LF1)
¢ Result = —12 VDC Level
¢ Result = Incorrect
Defective Drive Assembly
Continue to Step 5
No +12 VDC Problem or
Open +12 VDC Trace
Continue to Step 6
Defective Filter LF1
Defective Power Supply or
Shorted Component
No —12 VDC Problem or
Open —12 VDC Trace
Continue to Step 8
Defective Filter LF1
Defective Power Supply or
Shorted Component
3-4
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 1.2 — TROUBLESHOOTING THE A500 SYSTEM RESET
By referring to this section, it is assumed that one or more of the reset signals from BASIC PRELIMINARY CHECKS,
STEPS 4 through 6 are incorrect.
1.2.1 INCORRECT (RST) RESET
(P) STEP |
(P) STEP 1.1
(P) STEP 1.2
Measure the signal 5 (KBRESET)* of IC US (GARY)
e Result = 0 VDC to +5 VDC shortly after system power up
© Result = Incorrect
Measure the signal on collector of transistor Q711 (2N3904)
¢ Result = 0 VDC to +5 VDC Level shortly after power up
© Result = Incorrect
Measure the signal on pin 3 (OUT) of IC U42 (555)
e Result = +5 VDC to 0 VDC Level shortly after power up
e Result = Incorrect
1.2.2 INCORRECT (RESET) OR (IORESET) RESET
(P) STEP 2
(P) STEP 3
(P) STEP 4
Measure the signal on pin 12 (RST)* of IC U37 (74LS32)
e Result = 0 VDC to +5 VDC shortly after power up
© Result = Incorrect
Measure the signal on pin 11 (RESET)* of IC U37 (74LS32)
e Result = 0 VDC to +5 VDC shortly after system power up
© Result = Incorrect
Measure the signal on pin 8 (IORESET)* of IC U37 (74LS32)
¢ Result = 0 VDC to +5 VDC Level shortly after power up
e Result = Incorrect
SECTION 1.3 — TROUBLESHOOTING THE A500 SYSTEM CLOCKS
1.3.1 INCORRECT (CLK) CLOCK
STEP 1
STEP 2
Measure the signal on pin 34 (28MHZ) of IC U2 (FAT AGNUS)
¢ Result = 28 MHZ Clock
© Result = Incorrect
Measure the signal on pin 38 (7MHZ) of IC U2 (FAT AGNUS)
¢ Result = 7 MHZ Clock
© Result = Incorrect
1.3.2 INCORRECT (CCK) CLOCK
STEP 3
Measure the signal on pin 28 (CCK) of IC US (GARY)
© Result = 3.58 MHZ Clock
¢ Result = Incorrect
1.3.3 INCORRECT (CCKQ) CLOCK
STEP 4
Measure the signal on pin 27 (CCKQ) of IC US (GARY)
© Result = 3.58 MHZ Clock
e Result = Incorrect
tou
1.3.4 INCORRECT (CDAC) CLOCK
STEP 5
Measure the signal on pin 26 (CDAC)* of IC U5 (GARY)
¢ Result = 7 MHZ Clock
¢ Result = Incorrect
*INDICATES ACTIVE LOW
A500 SERVICE MANUAL
Continue to Step 2
Continue to Step 1.1
KBRESET OK or Open Reset
Trace
Continue to Step 1.2
Defective Q711, US Keyboard,
Connector CN13
Defective U42 or
Associated Circuitry
Continue to Step 3
Defective U5, U1, U2, U37
RESET OK or Open Reset Trace
Defective U37, U7, U8
IORESET OK or Open Reset Trace
Defective U37 Connector CN7
Continue to Step 2
Defective X1, U2
CLK OK or Open Trace
Defective U2, U1, U4
Defective U33, U4
Defective US, U2, U3, U4, U33
Defective U33
Defective US, U2, U3, U33
Defective U33
Defective US, U2, U4, U33
3-5
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 2 — TROUBLESHOOTING THE MOTOROLA 68000 PROCESSOR
All initial power up signals must be processed by the 68000. In order for the correct power up sequence to take place,
the 68000 control signals must be operating correctly.
Although the 68000 will probably initialize with signals of +2.5 VDC levels or above, a problem exists if control
signals do not reach close to the +5 VDC levels.
STEP 1 Measure the signal on pin 17 (HLT)* of IC U1 (68000)
¢ Result = +5 VDC Level Continue to Step 1.1
e Result = Incorrect Defective U1, US
(P) STEP 2. Measure the signal on pin 18 (RST)* of IC U1 (68000)
e Result = 0 VDC to +5 VDC shortly after power up Continue to Step 1.2
¢ Result = Incorrect See Section 1.2 Troubleshooting
the A500 System Reset
(P) STEP 3 Measure the signal on pin 7-8 (UDS)*, (LDS)* of IC U1 (68000)
¢ Result = +5 VDC Level should start pulsing on initialization Continue to Step 1.3
e Result = Incorrect pin 7 (UDS) Defective U1, US, U2
© Result = Incorrect pin 8 (LDS) Defective U1, U5
(P) STEP 4 Measure the signal on pin 9 (R/_W)* of IC U1 (68000)
© Result = +5 VDC Level with Negative Pulsing Continue to Step 1.4
© Result = Incorrect Defective U7, U8, U1, US, U2
STEP 5 Measure the signal on pin 6 (AS)* of IC UI (68000)
¢ Result = +5 VDC Sawtooth Continue to Step 1.5
© Result = Incorrect Defective U1, US, U2
STEP 6 Measure the signal on pin 10 (DTACK)* of IC U1 (68000)
© Result = +5 VDC Square Wave Continue to Step 1.6
¢ Result = Incorrect Defective U1, U5
STEP 7 Measure the signal on pin 19,21 (VMA)* (VPA)* of IC U1 (68000)
© Result = +5 VDC Level with Negative Pulse Continue to Step 1.7
¢ Result = Incorrect pin 19 (VMA) Defective U1
e Result = Incorrect pin 21 (VPA) Defective U1, US
STEP 8 Measure the signal on pin 15 (CLK) of IC U1 (68000)
© Result = 7 MHZ Clock Continue to Step 1.8
See Section 1.3 Troubleshooting
© Result = Incorrect
the A500 System Clock
STEP 9 Measure the signal on pin 20 (E) of IC U1 (68000)
¢ Result = +5 VDC Square Wave Continue to Step 10
© Result = Incorrect Defective U7, U8, U1
(P) STEP 10 Measure the signal on pin 26,28 (FC2), (FCO) of IC U1 (68000)
¢ Result = +5 VDC to 0 VDC with positive pulses Continue to Step 11
* Result = Incorrect (Either or Both) Defective U1, RP102
(P) STEP 11 Measure the signal on pin 27 (FC1) of IC U1 (68000)
¢ Result = +5 VDC on power up, then to 5 VDC pulsing Continue to Step 12
¢ Result = Incorrect Defective U1, RP102
STEP 12 Measure the signal on pin 23 (IPL2)* of IC U1 (68000)
¢ Result = +5 VDC Level Continue to Step 13
¢ Result = Incorrect Defective U1, U3, RP102
“INDICATES ACTIVE LOW
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 2 — TROUBLESHOOTING THE MOTOROLA 68000 PROCESSOR (Continued)
STEP 13 Measure the signal on pin 24,25 (IPL1)*, (IPL0O)* of IC U1 (68000)
STEP 14
© Result
© Result
= +5 VDC with Negative Pulses
= Incorrect (Either or Both)
A500 SERVICE MANUAL
Continue to Step 14
Defective U1, U3, RP102
Measure the signals on pins 22 (BEER)*, 12 (BGACK)*, 11 (BG)*, 13 (BA) of IC U1 (68000)
© Result
© Result
¢ Result
= +5 VDC Level
= Incorrect pin 12 (BGACK)
Incorrect pins 22, 11, 13
SECTION 3 — TROUBLESHOOTING THE A500 SYSTEM 8520 CIA’s
Measure the signals on pins 23 (CS)*, 23 (CS)* of IC U7, U8 (8520)
STEP 1
STEP 1.1
STEP 1.2
STEP 1.3
STEP 2
STEP 3
STEP 4
STEP 5
STEP 6
STEP 7
e Result
© Result
= +5 VDC Level with Negative Pusling
= Incorrect (U7 or U8)
Measure the input to pin 5 (VMA)* of IC U37 (74LS32)
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
= +5 VDC Level with Negative Pulsing
= Incorrect
the input to pin 4 (A13) of IC U37 (74LS32)
= 5 V Pulsing Address
= Incorrect
the input to pin 1 (A12) of IC U37 (74LS32)
= 5 V Pulsing Address
= Incorrect
the input to pin 22 (W)* of IC U8 (8520)
= 5 V Pulsing - Should Stabilize on Work Bench
Prompt display
= Incorrect
the signal on pin 25 (E) of IC U7 and U8 (8520)
= 5 V Pulsing
= Incorrect
the signal on pin 21 (INT)* of IC U7 (8520)
= +5 VDC Level - Negative Pulses during disk load
= Incorrect
the signal on pin 21 (INT)* of IC U8 (8520)
= +5 VDC Level
= Incorrect
the signal on pin 19 (TICK)* of IC U7 (8520)
= Standard Vertical Sync
= Incorrect
the signal on pin 19 (TICK)* of IC U8 (8520)
= Standard Horizontal Sync
= Incorrect
*INDICATES ACTIVE LOW
Continue to Section 2.1
Defective U1, US, RP104
Defective U1, RP104
Continue to Step 2
Continue to Step 1.1
Continue to Step 1.2
Defective U1, U37, RP102
Defective U37, U7
U1, U2, U6
Defective U37, U8
U1, U2, U6
Continue to Step 3
Defective U8, U7, UI, US, U2
Continue to Step 4
Defective U7, U8, U1
Continue to Step 5
Defective U8, U3
Continue to Step 6
Defective U7, U3
Continue to Step 7
Defective U2, U7
Continue to Step 8
Defective U2, U8
3-7
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 4 — TROUBLESHOOTING THE A500 SYSTEM VIDEO
If all listed signals seem to be correct, the processor should be up and the system should be able to produce video
information.
To make troubleshooting of the system video easier, both Analog RGB and Digital RGBI, as well as Composite Mode
should be checked for proper operation.
IMPORTANT: USE A KNOWN GOOD MONITOR AND CABLE
SECTION 4.1
STEP 1
STEP 2
SECTION 4.2
STEP 1
STEP 2
STEP 3
SECTION 4.3
STEP 1
STEP 2
STEP 3
— INCORRECT OR NO DIGITAL VIDEO DISPLAYED
Measure the digital outputs (BO-B7) of IC U40, (BO-B3) of IC U41 (74HCT245)
¢ Result = Buffered RGBI Video Defective RP402, CN9
© Result = Incorrect Continue to Step 2
Measure the digital inputs (A0-A7) of IC U40, (A0-A3) of IC U41 (74HCT245)
e Result = Digital RGB Video Defective U40, U41, HY1
e Result = Incorrect Defective U4, U40, U41
— INCORRECT OR NO ANALOG RGB VIDEO DISPLAYED
Measure the Analog Outputs (AR, AG, AB) of IC HY! (VIDEO HYBRID)
e Result = Analog RGB Video Defective EMI 431-433, CN9
© Result = Incorrect Continue to Step 2
Measure the Digital Outputs (BO-B7) of IC U40, (BO-B3) of IC U41 (74HCT245)
e Result = Buffered RGBI Video Defective HY1
© Result = Incorrect Continue to Step 3
Measure the Digital Inputs (A0-A7) of IC U40, (A0-A3) of IC U41 (74HCT245)
© Result = Digital RGB Video Defective U40, U41
© Result = Incorrect (U40) Defective U4, U40, U41
— INCORRECT OR NO COMPOSITE VIDEO DISPLAY
Measure the Composite Output (Comp) of IC HY! (VIDEO HYBRID)
¢ Result = Composite Video and Sync Defective EMI 435, CN10
¢ Result = Incorrect (Video) Continue to Step 2
¢ Result = Incorrect (Sync) Continue to Section 3.6
Measure the Digital Outputs (BO-B7) of IC U40, (BO-B3) of IC U41 (74HCT245)
¢ Result = Buffered RGBI Video Defective HY!
© Result = Incorrect Continue to Step 3
Measure the Digital Inputs (A0-A7) of IC U40, (A0-A3) of IC U41
¢ Result = Digital RGBI Video Defective U40, U41
© Result = Incorrect Defective U4, U40, U41
SECTION 4.4 — INCORRECT OR NO RGB VERTICAL SYNC
STEP 1
Measure the signal on pin 5 of RP403 (RESISTOR PACK)
¢ Result = Standard Vertical Sync Defective RP403, CN9
¢ Result = Incorrect Defective U2, RP403
SECTION 4.5 — INCORRECT OR NO RGB HORIZONTAL SYNC
STEP 1
Measure the signal on pin 3 of RP403 (RESISTOR PACK)
¢ Result = Standard Horizontal Sync Defective RP403, CN9
e Result = Incorrect Defective U2, RP403
3-8
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 4.6 — INCORRECT OR NO COMPOSITE SYNC
STEP 1 Measure the signal on the output (B7) of IC U41 (74HCT245)
e Result = Standard Composite Sync Defective HY1
¢ Result = Incorrect Continue to Step 2
STEP 2 Measure the signal on the input (A7) of IC U41 (74HCT245)
e Result = Standard Composite Sync Defective U4]
¢ Result = Incorrect Defective U2, U4, U41
SECTION 5 — TROUBLESHOOTING THE A500 SYSTEM INTERNAL DRIVE CIRCUITS
If video information is being displayed, but errors are encountered while trying to read from or write to the Internal
Drive, the control signals to this circuitry should be checked for proper operation.
IMPORTANT: USE A KNOWN GOOD DRIVE ASSEMBLY TO ELIMINATE
THE DRIVE ITSELF AS THE POSSIBLE CAUSE OF ERRORS
SECTION 5.1 — DRIVE MOTOR DOES NOT OPERATE CORRECTLY
STEP 1 Measure the signal on pin 7 (MTR)*, 16 (SEL)* of IC US (GARY)
e Result = High to Low Toggle = Motor On Continue to Step 2
Stays High = Motor Off
© Result = Incorrect Defective U8, US
STEP 2 Measure the signal on pin 46 (MTRON) of IC US (GARY)
e Result = High = Motor On Continue to Step 3
Low = Motor Off
© Result = Incorrect Defective US, U36
STEP 3 Measure the signal on pin 6 (MTRO)* of IC U36 (74LS38)
e Result = Low = Motor On Continue to Step 4
High = Motor Off
© Result = Incorrect Defective U36, Q503, CN11
STEP 4 Measure the signal on pin 12 (SIDE)* of IC U8 (8520)
e Result = High to Low Toggle = Motor On Continue to Step 5
Stays High = Motor Off
e Result = Incorrect Defective U8, CN11
STEP 5 Measure the signal on pin 10 (STEP)* of IC U8 (8520)
¢ Result = High Level with Negative Pulsing during motor on Continue to Step 6
and head step time
¢ Result = Incorrect (U40) Defective U8, CNII
STEP 6 Measure the signal on pin 24 (INDEX)* of IC U8 (8520)
¢ Result = High Level with Wide Negative Index Pulses Continue to Step 7
¢ Result’ = Incorrect Defective U8, CN11
STEP 7 Measure the signal on pin 7 (RDY)* of IC U7 (8520)
¢ Result = High to Low Toggle = Motor On Continue to Step 8
High Level = Motor Off
¢ Result = Incorrect Defective U7, CN11
STEP 8 Measure the signal on pin 6 (TRKO)* of IC U7 (8520)
¢ Result = High to Low Toggle each time disk is inserted Continue to Step 9
¢ Result = Incorrect Defective U7, CN11
* INDICATES ACTIVE LOW
3-9
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 5.1 — TROUBLESHOOTING THE A500 SYSTEM INTERNAL DRIVE CIRCUITS (Continued)
STEP 9
STEP 10
STEP 11
STEP 12
Measure the signal on pin 5 (WPROT)* of IC U7 (8520)
e Result = Write-Protect OFF (Tab Closed - High Level)
Write-Protect ON (Tab Open - High or Low
Toggle) each time disk is inserted
© Result = Incorrect
Measure the signal on pin 4 (CHNG)* of IC U7 (8520)
e Result = High Level with Negative Pulsing each time disk
is removed from drive
© Result = Incorrect
Measure the signal on pin 3 (LED)* of IC U7 (8520)
e Result = +5 VDC to 0 VDC Level when Power LED
comes on
© Result = Incorrect
Measure the signal on pin 37 (DKRD)* of IC U3 (PAULA)
e Result = +5 VDC Level with Negative Pulsing during
disk read
© Result = Incorrect
ERROR DURING DISK WRITE
STEP 13
STEP 13.1
STEP 13.2
STEP 14
STEP 14.1
STEP 14.2
Measure the signal on pin 8 (DKWDB)* of IC U36 (74LS38)
© Result = +5 VDC Level with Negative Pulsing
© Result = Incorrect
Measure the signal on pin 45 (DK WDB) of IC US (GARY)
¢ Result = 0 VDC Level with Positive Pulsing
e Result = Incorrect
Measure the signal on pin 38 (DKWD)* of IC U3 (PAULA)
¢ Result = +5 VDC Level with Negative Pulsing
© Result = Incorrect
Measure the signal on pin 11 (DKWEB)* of IC U36 (74LS38)
¢ Result = High to Low Toggle during disk write
¢ Result = Incorrect
Measure the signal on pin 44 (DK WEB) of IC US (GARY)
¢ Result = Low to High Toggle during disk write
¢ Result = Incorrect
Measure the signal on pin 39 (DKWE) of IC U3 (PAULA)
© Result = Low to High Toggle during disk write
© Result = Incorrect
*INDICATES ACTIVE LOW
Continue to Step 10
Defective U7, CN11
Continue to Step 11
Defective U7, CN11
Replace Socketed ICs
Defective U7, Q502, U33
Continue to Step 13
Defective U3, CN11
Continue to Step 14
Continue to Step 13.1
Defective U36
Continue to Step 13.2
Defective U5
Defective U3, US
Continue to Step 15
Continue to Step 14.1
Defective U36, CN9
Continue to Step 14.2
Defective US
Defective U3, US
A500 SERVICE MANUAL
3-10
A500 SYSTEM TROUBLESHOOTING (Continued)
A500 SERVICE MANUAL
SECTION 6 — TROUBLESHOOTING THE A500 SYSTEM CONTROL PORTS
If the system reaches normal power up and errors are encountered while trying to access the icons or erratic mouse
or joystick operation is encountered, the control port circuitry should be checked for proper operation.
Use a standard joystick for testing these ports.
IMPORTANT: USE A KNOWN GOOD MOUSE OR JOYSTICK
TO ELIMINATE THIS AS THE POSSIBLE CAUSE OF ERRORS
CONTROL PORT 0 ERROR — CN1
STEP 1 Measure the input on pin 2 (1A) of IC U1I5 (72LS157)
¢ Result = +5 VDC to 0 VDC = UP
© Result = Incorrect
STEP 2. Measure the input on pin 3 (1B) of IC U15 (74LS157)
e Result = +5 VDC to 0 VDC = LEFT
© Result = Incorrect
STEP 3. Measure the input on pin 5 (2A) of IC U1S (74LS157)
e Result = +5 VDC to 0 VDC = DOWN
© Result = Incorrect
STEP 4 Measure the input on pin 6 (2B) of IC U15 (74LS157)
© Result +5 VDC to 0 VDC = RIGHT
© Result = Incorrect
STEP 5 Measure the output on pin 2 (FIREO) on EMI415
e Result = +5 VL to 0 VDC = FIRE
¢ Result = Incorrect
STEP 6 Measure the output on pin 4 (1Y) of IC UI5 (74LS157)
¢ Result = +5 VDC Level = CENTER
Multiplexed Output = UP/LEFT
¢ Result = Incorrect
STEP 7 Measure the output on pin 7 (2Y) of IC U15 (74LS157)
¢ Result = +5 VDC Level CENTER
Multiplexed Output = RIGHT/DOWN
¢ Result = Incorrect
ot
CONTROL PORT 1 ERROR — CN2
STEP 1 Measure the input on pin 11 (3A) of IC U15 (74LS157)
¢ Result = +5 VDC to 0 VDC = UP
¢ Result = Incorrect
STEP 2 Measure the input on pin 10 (3B) of IC U15 (74LS157)
© Result = +5 VDC Level to 0 VDC = LEFT
¢ Result = Incorrect
STEP 3 Measure the input on pin 14 (4A) of IC U15 (74LS157)
¢ Result = +5 VDC to0 VDC = DOWN
© Result = Incorrect
STEP 4 Measure the input on pin 13 (4B) of IC UI5 (74LS157)
¢ Result +5 VDC to 0 VDC = RIGHT
© Result = Incorrect
not "ou
Continue to Step 2
Defective U15, EMI411, RP401, CN1
Continue to Step 3
Defective U15, EMI412, RP401, CNI
Continue to Step 4
Defective U15, EMI413, RP401, CNI1
Continue to Step 5
Defective U15, EMI414, RP401, CNI1
Continue to Step 6
Defective EMI415, U7, CN1
Continue to Step 7
Defective U15, U4, RP404, RP405
Control Port 0 OK
Defective U15, U4, RP404, RP405
Continue to Step 2
Defective U15, EMI421, RP401, CN2
Continue to Step 3
Defective U15, EMI422, RP401, CN2
Continue to Step 4
Defective U15, EM1423, RP401, CN2
Continue to Step 5
Defective U1S5, EMI424, RP401, CN2
3-11
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 6 — TROUBLESHOOTING THE A500 SYSTEM CONTROL PORTS (Continued)
STEP 5 Measure the output on pin 2 (FIRE1) of EMI425
¢ Result = +5 VDC to 0 VDC = FIRE Continue to Step 6
© Result = Incorrect Defective EM1425, U7, CN2
STEP 6 Measure the output on pin 9 (3Y) of IC U15 (74LS157)
e Result = +5 VDC Level = CENTER Continue to Step 7
Multiplexed Output = UP/LEFT
e Result = Incorrect Defective U15, U4, RP404, RP405
STEP 7 Measure the output on pin 12 (4Y) of IC U15 (74LS157)
e Result = +5 VDC Level = CENTER Control Port 1 OK
Multiplexed Output = RIGHT/DOWN
© Result = Incorrect Defective U15, U4, RP404, RP405
SECTION 7 — TROUBLESHOOTING THE A500 SYSTEM KEYBOARD CIRCUITS
If the LED located on the Shift/Lock key goes into a flash code on power up, a failure in the keyboard circuitry is norm-
ally indicated. The circuitry located on the physical keyboard is normally at fault when this condition is encountered.
FLASH CODE FAILURE CHART
1 FLASH = ROM (Internal to the Keyboard Processor)
2 FLASHES = RAM (Internal to the Keyboard Processor)
3 FLASHES = WATCHDOG TIMER (IC 74LS123 or Associated Circuitry)
If no flashes are displayed or the keyboard is not the cause of the problem, troubleshooting of the main PCB keyboard
circuitry will be necessary.
KEYBOARD CONNECTOR (CN13) PINOUTS — FROM FRONT OF PCB
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8
* * * * * * * *
KBDATA CLOCK RESET +5V KEY GROUND STATUS INUSE
STEP 1 Measure the signal on pins 2 (KBDATA)*, 1 (KBCLOCK)* of Connector CN13
© Result = +5 VDC Level - Negative Pulsing when . Continue to Step 2
key is depressed
© Result = Incorrect Defective U7, RP501, CN13
STEP 2 Measure the signal on pin 3 (KBRESET)* of Connector CN13
¢ Result = 0 VDC to +5 VDC shortly after system power up = Continue to Step 3
¢ Result = Incorrect Refer to Section 1.2 — A500
System Reset
STEP 3 Measure the signal on pin 7 (STATUS) of Connector CN13
e Result = 0 VDC to +5 VDC when Power LED comes on Continue to Step 4
© Result = Incorrect Continue to Step 3.1
STEP 3.1 Measure the signal on pin 3 (LED)* of IC U7 (8520)
¢ Result = +5 VDC to 0 VDC when Power LED comes on Defective Q502 or Associated
Circuitry
¢ Result = Incorrect Defective U7, Q502, U38
STEP 4 Measure the signal on pin 8 (INUSE) of Connector CN13
* Result = 0 VDC Level - Toggles High each time disk inserted Keyboard OK
¢ Result = Incorrect Continue to Step 4.1
STEP 4.1 Measure the signal on pin 6 (MTRO)* of IC U36 (74LS38)
¢ Result = Low = Motor On Defective Q503 or Associated
High = Motor Off Circuitry
¢ Result = Incorrect Defective U36, Q503
*INDICATES ACTIVE LOW 3-12
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 8 — TROUBLESHOOTING THE A500 SYSTEM AUDIO CIRCUITS
In order to determine failures in the audio circuitry it is necessary to generate some type of audio output while check-
ing signals. Selecting the Music Icon from the Extras Disk will work to accomplish this.
If both channels are failing it is recommended that a Dual Trace Scope be used for audio troubleshooting. If only
one channel is failing, using a single trace of the scope should be sufficient.
INCORRECT LEFT AUDIO CHANNEL
Measure the signal on pin 31 (LEFT) of IC U3 (PAULA)
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 6
STEP 7
© Result
e Result
Measure the input to pin 13 (—) of IC U14 (LF347)
© Result
e Result
Measure
¢ Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
¢ Result
e Result
Measure
© Result
© Result
= Approximately 100 mV Audio
= Incorrect
= Approximately 100 mV Audio
= Incorrect
the output on pin 14 of IC U14
= Approximately 1-2 V Audio
= Incorrect
the input to pin 3 (+) of IC U14
= Approximately 1-2 V Audio
= Incorrect
the output on pin 1 of IC U14
= Approximately 1-2 V Audio
= Incorrect
the signal on pin 1 of EMI302
= Approximately 100 mV Audio
= Incorrect
the signal on pin 2 (LEFT), of EMI302
= Approximately 200 mV Audio
= Incorrect
INCORRECT RIGHT AUDIO CHANNEL
Measure the signal on pin 30 (RIGHT) of IC U3 (PAULA)
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 6
STEP 7
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
Measure
© Result
© Result
= Approximately 100 mV Audio
= Incorrect
the input to pin 9 (—) of IC U14 (LF347)
= Approximately 100 mV Audio
= Incorrect
the output on pin 8 of IC U14 (LF347)
= Approximately 1-2 V Audio
= Incorrect
the input to pin 5 (+) of IC U14 (LF347)
= Approximately 1-2 V Audio
= Incorrect
the output on pin 7 of IC U14 (LF347)
= Approximately 1-2 V Audio
= Incorrect
the signal on pin 1 of EMI303
= Approximately 100 mV Audio
= Incorrect
the signal on pin 2 (RIGHT) of EMI303
= Approximately 200 mV Audio
= Incorrect
A500 SERVICE MANUAL
Continue to Step 2
Defective U3, U14, EMI306
Continue to Step 3
Defective EMI306, U14 or Associated
Circuitry
Continue to Step 4
Defective U14 or Associated Circuitry
Continue to Step 5
Defective R322, R323
Continue to Step 6
Defective U14 or Associated Circuitry
Continue to Step 7
Defective C324, C325, R324, R325, EMI302
Defective CN4
Defective EMI302, CN3
Continue to Step 2
Defective U3, U14, EMI305
Continue to Step 3
Defective EMI305, U14 or Associated
Circuitry
Continue to Step 4
Defective U14 or Associated Circuitry
Continue to Step 5
Defective R332, R333
Continue to Step 6
Defective U14 or Associated Circuitry
Continue to Step 7
Defective C334, C335, R334, R335, EMI303
Audio OK or Defective CN3
Defective EM1303, CN3
3-13
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 9 — TROUBLESHOOTING THE A500 SYSTEM CENTRONICS PORT
When all control signal to the 8520 CIAs are confirmed good, (See Section 2), the Centronics Parallel Port should
be operational. To verify proper operation of this port it is necessary to connect a printer and load software to access
it. Signals should be measured as the printer is being accessed.
STEP 1
STEP 1.1
STEP 2
STEP 2.1
STEP 3
STEP 3.1
STEP 4
Measure the signals on pin 2 (D0-D7) of EMI512 through EMI519
e Result = +5 VDC Level on normal power up will become Continue to Step 2
active when the printer is accessed
e Result = Incorrect Continue to Step 1.1
Measure the signals on pin 1 (PBO-PB7) of EMI512 through EMI519
¢ Result = +5 VDC Level on normal power up will become Defective EMI512 - EMI519
active when the printer is accessed
e Result = Incorrect Defective U7, EMI512 -
EMIS519
Measure the signals on pins 2 (STROBE)*, (ACK)* of EMI511, EMIS521
¢ Result = +5 VDC Level on normal power up will become Continue to Step 3
active when the printer is accessed
¢ Result = Incorrect Continue to Step 2.1
Measure the signals on pins | (PC)*, (F)* of EMIS11, EMIS21
e Result = +5 VDC Level on normal power up will become Defective EMI511, EMI521
active when the printer is accessed
e Result = Incorrect Defective U7, EMIS11,
EMIS521
Measure the signals on pin 2 (BUSY), (POUT), (SEL) of EMI522 - EMI524
© Result = +5 VDC Level on normal power up will become Continue to Step 4
active when the printer is accessed
e Result = Incorrect Continue to Step 3.1
Measure the signals on pin 1 (PAO-PA2) of EMI522 - EMI524
© Result = +5 VDC Level on normal power up will become Defective EMI522 - EMI524
active when the printer is accessed
¢ Result = Incorrect Defective U8, EMIS522 -
EMI524
All outputs seem correct Replace U7, U8 and check
Connector CN7
SECTION 10 — TROUBLESHOOTING THE A500 SYSTEM RS232 PORT
When all control signal to the 8520 CIAs are confirmed good, (See Section 2), the RS232 Serial Port should be opera-
tional. To verify proper operation of this port it is necessary to connect a printer and load software to access it. Signals
should be measured as the printer is being accessed.
STEP 1
STEP 1.1
Measure the signals on pins 2 (TxD), (RTS) of EMI532 through EMI533
¢ Result = +5 VDC Level on normal power up will become Continue to Step 2
active when the printer is accessed
¢ Result = Incorrect Continue to Step 1.1
Measure the signals on pins 4, 9 (PA6), (TxD)* of IC U38 (1488)
¢ Result = +5 VDC Level on normal power up will become Defective U38, EMI533,532
active when the printer is accessed
¢ Result = Incorrect (PA6) Defective U8, U38
© Result = Incorrect (TxD) Defective U3, U38
*INDICATES ACTIVE LOW
: 3-14
A500 SERVICE MANUAL
A500 SYSTEM TROUBLESHOOTING (Continued)
SECTION 10 — TROUBLESHOOTING THE A500 SYSTEM RS232 PORT (Continued)
STEP 2. Measure the signal on pin 1 (DTR) of EMIS531
e Result = +5 VDC Level on normal power up will become Continue to Step 3
active when the printer is accessed
e Result = Incorrect Continue to Step 2.1
STEP 2.1 Measure the signal on pin 12 (PA7) of IC U38 (1488)
e Result = +5 VDC Level on normal power up will become Defective U38, EMI531
active when the printer is accessed
© Result = Incorrect Defective U8, U38
STEP 3 Measure the signals on pins 5-7 (PA3-PAS) of IC U8 (8520)
e Result = +5 VDC Level on normal power up will become Continue to Step 4
active when the printer is accessed
© Result = Incorrect Defective U39, U8, EMI535 -
EMI537
STEP 4 Measure the signal on pins 3 (RxD)* of IC U39 (1489)
e Result = +5 VDC Level on normal power up will become Continue to Step 5
active when the printer is accessed
e Result = Incorrect Defective 39, U3
STEP 5 __ All signals seem correct Replace U8, U3, U38, U39
*INDICATES ACTIVE LOW
3-15
SECTION 4
PARTS
A500 SERVICE MANUAL
SERVICE PARTS REFERENCE DIAGRAM
TOP CASE
312505-01
MOUSE
327124-02
KEYBOARD ASSY
312502-01
POWER SUPPLY
312503-01
DISK DRIVE ASSY
312594-01
— INCLUDES —
* POWER CABLE
252480-01
° CONN CABLE
252481-02
* 3.5 FOD PANASONIC
327142-01
© BUTTON (PANASONIC)
328117-01
* 3.5 FOD (CHINON)
312554-01
A501 RAM/CLOCK
EXP ASSY
312600-01
— INCLUDES —
* A501 TOP SHIELD
312606-01
¢ ASO1 INSULATION
312607-01
° ASO1 BOTTOM SHIELD
312608-01
TOP SHIELD
312504-01
PCB ASSY NTSC
312510
RF SHIELD
EXPANSION
327038-01
A501 RAM/CLOCK
EXP PCB ASSY
312604-01
BOTTOM CASE
312506-01 aa @ CN9-23P MALE VIDEO - 327032-032 U3, IC PAULA 8364 R7 - 252127-01
312589-01 @® CN8-5P SQUARE POWER - 252167-01 @® US, IC GARM - 318072-01
EXPANSION ® CN7-25P FEMALE-CENTRONICS - 327033-05 (2 U2, 1¢ FAT AGNUS 8370 NTSC - 318070-01
as pee BOTTOM SHIELD @ CN6-25P MALE - RS232 - 327032-05 «3 U6, IC ROM - 315093-02 (1.3)
312590-01 ® CNS5-23P FEMALE - DISK DRIVE - 327033-03 GT1 - BATTERY, NICAD 3.6V 60 WATT - 380393-01
@® HY1-VIDEO HYBRID - 390229-01 (®) Y2 - CRYSTAL 32-768 KHZ - 900560-01
Masse iay (4) RAM SC ieION @@® w7, us - 102520 ns - 318029-02 US - IC REAL TIME CLK OKI MSM6242B - 318073-01
312519-01 @® U4, IC DENISE 8362 R8 - 252126-01
4-1
A500 MAJOR COMPONENT PARTS LIST
Power Cable FDD
Conn Cable FDD
Keyboard Assy — USA/Canada
Power Supply
Top Shield
Top Case
Bottom Case
PCB Assy — NTSC
RAM Expansion Door
Floppy Disk Drive (Chinon)
Insulation Sheet
Bottom Shield
Disk Drive Assy
Expansion Cover
A501 RAM/Clock PCB Assy (With Shields)
A501 RAM/CLK PCB Assy (PCB Only)
A501 Top Shield
A501 Insulation Sheet
A501 Bottom Shield
Service Manual
Users Guide, DOS Manual
Amiga Basic Diskette
Workbench Diskette
RF Shield Expansion
Amiga Basic Manual
Mouse
Floppy Disk Drive (Panasonic)
Button (Panasonic)
Plate Logo
Rubber Feet
C - Indicates Commodore Stocked Part Number
QAANDIANDAIAANAANAINAANAANAANAAADA
QIAANDAAAANAAANO
252480-01
252481-02
312502-01
312503-01
312504-01
312505-01
312506-01
312510-01
312519-01
312554-01
312589-01
312590-01
312594-01
312595-01
312600-01
312604-01
312606-01
312607-01
312608-01
314981-01
317100-01
317488-02
317608-01
327038-01
327102-01
327124-02
327142-01
328117-01
380133-03
950150-03
A500 SERVICE MANUAL
COMPONENT PARTS LIST
PCB ASSEMBLY #321510, A500, REV. 5
321510-05 PCB ASSY, A500 NTSC 321510-06 PCB ASSY, A500 PAL
Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore.
Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips,
Transistors, etc. are available in manual form through the Service Department, order #314000-01.
M68000, 8 MHz
FAT AGNUS, 8370R3 NTSC
FAT AGNUS, 8371R1, PAL
PAULA, 8364R7
DENISE, 8362R8
GARY 5719
8520R4
ROM, KICKSTART V1.3
256K X 1 BIT DYNAMIC RAM
256K X 1 BIT DYNAMIC RAM
47K OHM, 5% 1/4W
1M OHM, 5% 1/4W
120 OHM, 5% 1/4W
10K OHM, 5% 1/4W
2.7K OHM, 5% 1/4W
470K OHM, 5% 1/4W
150 OHM, 5% 1/4W
EMI411-EMI417,
EMI421-EM1427
FB802,FB101
EMI411-EMI417,
EMI421-EMI427,
EMI402-EMI431-
EMI435
EMI301-EMI303,
EMI401-EMI405,
EMI FILTER, 100 pf
EMI431-EMI435,
EMIS511-EMI538,
EMI601-EMI61!-
EMI626,EMI701-
EMI704
EMI101,EMI302,
EMI303,EMI305,
DENISE, 8362R6
DRAM, 256K X 1 BIT, 80ns
DIN, 5 PIN, SQUARE, FEMALE
D-SUB, 9 PIN, MALE, RA, SOLDER-IN
D-SUB, 23 PIN, MALE, RA, SOLDER-IN
D-SUB/23PIN/FEMALE/RA/SOLDER-IN
D-SUB/25PIN/MALE/RA/SOLDER-IN
D-SUB/25PIN/FEMALE/RA/SOLDER-IN
RCA JACK, BLACK
RCA JACK, WHITE
RCA JACK, YELLOW
RCA JACK, METAL
HEADER, 4PIN, POLARIZED, SIL
HEADER, 8PIN, SIL
HEADER, 34PIN, DIL
EMI FILTER, 100 pf
EMI431-EMI1435,
EMIS511-EMI524,
EMI531-EMI538,
EMI601,EMI611-
EMI626,EMI702-
EMI704
EMI101,EMI302,
EMI303,EMI305,
EMI306,EMI403-
EMI407,EMI511-
EMI524,EMI531-
EMI538,EMI601,
EMI602,EMI611-
EMI626,EM1701,
EMI FILTER, 100 pf
NETWORK, 10K X 9 10PIN
NETWORK, 22 OHM X 5, 10PIN
NETWORK, 47 OHM X 4, 8PIN
NETWORK, 68 OHM X 4, 8PIN
NETWORK, 68 OHM X 5, 10PIN
NETWORK, 120 OHM X 5, 6PIN
NETWORK, 470 OHM X 7, 8PIN
NETWORK, 4.7K X 9, 1OPIN
39 pF, MLC, AXIAL, NPO
100 pF, MLC, AXIAL, NOP
1000 pF MLC AXIAL X7R
1000 pF MLC AXIAL X7R
3900 pF MLC AXIAL X7R
6800 pF MLC AXIAL X7R
.01 uF MLC AXIAL ZS5U
.01 uF MLC AXIAL Z5U
.047 uF MLC AXIAL X7R
.1] uF MLC AXIAL Z5U
CA11-C413,C421-C423
C323,C333
C322,C332
C410,C412,C801,C713
C€308,C713
C311-C314
C7,€8,C10,C11-C13,
C15,C33-C37,C39,
C321,C331,C711,
C701(-01 & -02)
C1-C6,C16-C32,C14,
CA0-C42,C301,C302,
€305,C501,CS02
€325,C335
€306,C712
€303,C30$,C307, C34
C812-C815, CR, CR
C307,C811
C401,C402
C702
NETWORK, 68 OHM X 4, 8PIN
ZERO OHM RESISTOR
1 OHM, 5% 1/4W
5.1 OHM, 5% 1/4W
10 OHM, 5% 1/4W
27 OHM, 5% 1/4W
47 OHM, 5% 1/2W
360 OHM, 5% 1/4W
390 OHM, 5% 1/4W
470 OHM, 5% 1/4W
1K OHM, 5% 1/4W
Wi1,W2
EM1301,EM1406
EM1401,R405,R406
R301,R302
R101,R102
EM1501,EM1503
R331,4321
901550-129
901550-64
901550-90
901600-15
901550-108
901550-57
901550-58
901550-01
.22 uF MLC AXIAL ZSU
901550-17
901550-23
901550-39
901550-19
901550-20
1.2K OHM, 5% 1/4W
2.7K OHM, 5% 1/4W
3.9K OHM, 5% 1/4W
4.7K OHM, 5% 1/4W
10K OHM, 5% 1/4W
.22 uF MLC AXIAL Z5U
10 uF ELECT RADIAL
22 uF ELECT RADIAL
47 uF ELECT RADIAL
100 uF ELECT RADIAL
3300 uF 10 V ELECT RADIAL
VARIABLE CAP 4.5-45 pf
R402,R403,R502-R504
R322,R323,R333,R339,
RS501,R505,R506
R703
901550-15 | 27K OHM, 5% 1/4W
A500 SERVICE MANUAL
COMPONENT PARTS LIST
PCB ASSEMBLY #321510, A500, REV. 5 (Continue)
MISCELLANEOUS (Continued)
TRANS 2N5S770 NPN OSC. Q701 904150-06 | SOCKET, 40 PIN DIP
TRANS 2N3904 NPN GP Q501,Q711 251313-01 | SOCKET, 48 PIN DIP
TRANS 2N3906 PNP GP Q502,Q503,Q301 251313-02 | SOCKET, 48 PIN DIP
TRANS JFET PN4302 MPF-102 Q321,Q331 390185-01 | SOCKET, 84 PIN PLCC
DIODE, 1N4148 DSs01 904150-10 | SOCKET, 64 PIN DIP
312519-01 | WIRE ASSEMBLY JUMPER
900462-37 | CAP 100 pF MLC AXIAL NOP
C101,R106,R107,R108,
R103,EMI402
C801-C803
U16-U31
U16-U31
U16-U31
390082-02
380223-03
390226-03
390226-05
VIDEO HYBRID 901550-94
VIDEO HYBRID 900463-36
LINE FILTER, 8PIN 320481-01
CHOKE, 3.3 uH 312511-01
CAP 0.01 uF MLC AXIAL Z5U
IC, 256K X 1 BIT DYNAMIC RAM
IC, 256K X 1 BIT DYNAMIC RAM
IC, 256K X 1 BIT DYNAMIC RAM
RES 68 OHM 5% 1/4W
CAP .047 uF MLC AXIAL X7R
SHRINK TUBING .50 IN. LG.
SCHEMATIC
A500 SERVICE MANUAL
COMPONENT PARTS LIST
PCB ASSEMBLY #312510, AMIGA A500, REV6A/7
312510-07 PCB ASSEMBLY, A500 NTSC —_312510-08 PCB ASSEMBLY, A500 PAL
Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore.
Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips,
Transistors, etc. are available in manual form through the Service Department, order #314000-01.
DIODES
INTERFACE MC1488 900850-01 | 1N4148 D501
INTERFACE MC1489 390017-01 | 1N914 D501
rien Sa eee
LINEAR NES555
MC68000 OMHz
MOS 5719 R2 GARY
MOS 8362 R8 DENISE
MOS 8364 R7 PAULA
MOS 8372 R3 AGNUS HR
EMI FILTER, 100pF
EMI FILTER, 150pF
EMI FILTER, 270pF
EMI FILTER, 470pF
E511-E519,EA21-E524,
E611-E626
E402,E434,E532,E534
E305,E306
EAIS-EA17,EA25-EA27,
EA41-E444,E520,E531,
E533,E535-E538
E302,E303,E411-E414,
EA21-E424
E101,E401,E403-E408,
E601,E602,E702-E704
E431-E433,R435
MOS 8520 R4 AMIGA CIA
EMI FILTER, 6800pF
EMI FILTER .OluF
FERRITE BEAD RADIAL
LINE FILTER
LONG FERRITE BEAD
FERRITE BEAD AXIAL E431-E433,EA35
VIDEO HYBRID
MOS 8370 R3 FAT AGNUS (NTSC)
MOS 8371 R1 FAT AGNUS (PAL)
390433-01 | MOS 8373 R2 DENISE HR
381099-04 | DRAM 256K X 4 120 nS
381099-02 | DRAM 256K X 4 100 nS
390254-01 | JFET MPF102/PN4302
902658-01 | NPN 2N3904
902707-01 | PNP 2N3906
RESISTORS
1/2W CF, 1 R309
1/2W CF, 4.7 R401,R405,R406,R408
1/2W CF, 47 E501-E503
1/4W CF, 10 R301,R302
1/4W CF, 27 R101,R102
1/4W CF, 47 R103-R107,R113
1/4W CF, 68 E104,E105
1/4W CF, 68 RIL1,R112,R114
1/4W CF, 68
1/4W CF, 100
1/4W CF, 150
1/4W CF, 150
1/4W CF, 360
C1-C8,C10-C19,C33- 1/4W CF, 390
C37,C39-C42,C301, 1/4W CF, IK R303-R305,R324,R334,
C302,C305,C325,C335, R713
C501,C502,C701,C804 1/4W CF, 2.7K R307,R502
C20-C23 1/4W CF, 4.7K R201,R202,R402,R403,
R503,R504
R306,R308,R322,R323,
R332,R333,R339,R501,
Q321,Q331
Q501,Q711
Q301,Q502,Q503
NOT LOADED
395093-02 | ROM 256K X 16 KICKSTART 1.3
MLC AXIAL NOP 47pF
MLC AXIAL NOP 47pF
MLC AXIAL NOP 47pF
MLC AXIAL X7R 1000pF
MLC AXIAL X7R 3900pF
MLC AXIAL X7R 6800pF
E102,E103,E106-3109
XC1-XC3
CA11-C413,C421-C423
C323,C333
C322,C332
C311-C314
C321,C331
C308,C713,C800-C803
MLC AXIAL X7R .047pF
MLC AXIAL X7R .1uF
MLC AXIAL ZSU .OluF
MLC AXIAL ZSU .1uF C71
MLC AXIAL ZS5U .33uF
NOT LOADED
ELECT ALUM RADIAL, 10uF 16V
ELECT ALUM RADIAL, 22uF 35V
ELECT ALUM RADIAL, 47uF 35V
ELECT ALUM RADIAL, 100uF 16V
ELECT ALUM RADIAL 470uF 16V
ELECT ALUM RADIAL 3300uF 10V
C306,C712
C303,C304,C324,C334
C821,C822
C811-C816
1/4W CF, 10K
1/4W CF, 47K
1/4W CF, 470K
1/4W CF, IM
RES PACK SIP PULLUP, 470 X 9
RES PACK SIP PULLUP, 4.7K X 9
RES PACK SIP PULLUP, 10K X 9
RES PACK SIP SERIES, 22 X 5
RES PACK SIP SERIES, 68 X 5
RES PACK SIP SERIES, 47 X 5
4PIN FLOPPY POWER
SPIN SQ DIN
8PIN SIL W/KEY
D-SUB/23PIN/FEMALE/DB23S
D-SUB/23PIN/MALE/DB23P
D-SUB/25PIN/FEMALE/DE25S
D-SUB/25PIN/MALE/DB25P
D-SUB/9PIN/MALE/DB9P
HEADER 34PIN W/KEY
HEADER S6PIN MALE RA
RCA JACK, YELLOW
RCA JACK, WHITE
RCA JACK, BLACK
8PIN SIL W/KEY
HEADER 34PIN W/KEY
RCA JACK, METAL
RCA JACK, METAL
SOCKET, 40PIN DIP
SOCKET, 48PIN DIP
SOCKET, 64PIN DIP
SOCKET, 84PIN PLCC
SOCKET, 48PIN DIP
OSCILLATOR, 28.37516NHz (PAL)
OSCILLATOR, 28.63636MHz (NTSC)
SCHEMATIC
4-4
A500 SERVICE MANUAL
COMPONENT PARTS LIST
PCB ASSEMBLY RAM EXPANSION/CLOCK
PCB ASSEMBLY #312604-04, A501, REV. 6C
Commodore part numbers are provided for reference only and do not indicate the availability of parts from Commodore.
Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Approved cross-references for TTL chips,
Transistors, etc. are available in manual form through the Service Department, order #314000-01.
CONNECTORS
DRAM 256K X 4 120nS 380311-05 | HEADER S6PIN FEMALE RA
DRAM 256K X 4 100nS DIODES
OKI MSM6242B REAL TIME CLOCK 900850-01 | SWITCHING IN4148 D912
TTL 74F27 TRIPLE 3-IN NOR 390017-01 | SWITCHING 1N914
TIL M4LSi63 BINARY COUN
TTL 74LS163 BINARY COUNTER MISCELLANEOUS
BATTERY NICD VARTA 3/60DK,
3.6V 60MAH
ae ay le CRYSTAL WATCH STYLE, 32768Hz
; FABRICATION DRAWING
PCB ARTWORK
SCHEMATIC
MLC AXIAL NPO 22pF
MLC AXIAL ZS5U .luF
MLC AXIAL ZSU .33uF
TRIMMER (YELLOW) 6.8-45pF
NOT LOADED
ELECT ALUM RADIAL 100uF 16V
ELECT TANTALUM RADIAL 4.7uF 16V
ELECT ALUM RADIAL 4.7uF 16V
cu
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ot
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FAB 312512
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TVANVW ADIAXAS 00SV
A500 Board Layout #312510, Rev. 5
—
i=]
Ty]
<x
Lu
ra
o
2
=)
=
=
Ce
[|L__# [ES
O
GUAY/GRR
oO
REV 5
l
I
ASSEMBLY 312604
U61
| a Coe Se
&
+
C903
C914
D912 R911
NOTE: PN #312604-03 — A501 RAM/CLOCK PCB ASSEMBLY — INCLUDES SHIELDS AND INSULATION
BOARD LAYOUT
A501 RAM/CLOCK EXPANSION
PCB ASSEMBLY #312604-03
TVANVW ADAMS 00SV
SECTION 5
SCHEMATICS
Schematic #312511-02, Rev. 5 A500 SERVICE MANUAL A500 SERVICE MANUAL
Sheet 1 of 9
Jumpers and Stuff Connectors
|TYPE DESCRIPTION |PAGE {LYPE DESCRIPTION
| |
|OBSP
[Keuboord Reset 7
[Memory Addr. CO vs 08 [2
Int. Memory ResO0 vs Ls
4
Mouse/Joustick 1
Mouse/Joustick 2
Right Audio Output
IRCA-J [Left Audio Output
S_|External Floppy
RS232 Serial Port
RTC Frequency Test
RTC Frequency Adjust |9
Floppy Signall7
Internel Floppy Power [8
Keuboord Connector 6
05/12/87
870222 06/16/87
870302 10709787
03/04/87
03/03/89
Signal Glossary
2 EFT/RIGHT [Left Right Audio (Audio)
Clock 2.5 LMTR_ Motor On (Floppy)
AL23:1) Processor Address Bus (68000) 2234729 MTRO Motor riyv (Flo
ACK Date Acknowledge (Perelle}] Port) 6 MOV/MOH Mouse O Quedrature V/H (Jo
AS Address Strobe (68000) 2st MIV/M1H Mouse | Quadreture V/H (Jousticks)
AUDIN Audio Input (RS232 Port) 4.6 OVL Overcloy ROM over RAM
AUDOUT | Audio Output (RS232 Jack J} 4 [Override System Decoding
B B or (68000) 7 PIXELSW Genlock Pixel Switch (Video)
Bus Grant (68000) Bet POTOX/OY | Pot Lines 0 X/Y (Jousticks)
B ent Acknowledge 12. POTLX/1Y Pot Lines | X/Y (Joysticks) 14,5
BLISS Blitter Slowdown (Chips]} 2 POUT Peper Out (Porellel Port) [Ul _—*(68000 [68000 Processor
BLIT Chip Memory Access (Chips) 247 PPD{7:0] Perallel Port Date (Pereallel Port) [U2 —«[8370 Fat Agnus - NTSC
BR B Request (68000) 2.7 RAMEN RAM Enoble (Chips) 2 Fat Agnus - PAL
SY Device Busy [Parolle) Port) 6 REGEN Chip Register Enoble (Chips) Agnus HR
223-9 |RASO/) Row Addre ebe (DRAM Pouloe
(Chips) 12.4.7 | RDY | Drive Ready (Floppy) Denise
CDAC 7.15909 MHz Quedrature Clock (Chips) | 2.5.7 RESE Generel Reset
1 dl RGA Reg er Address Bus hip oru
LCLKRD/WR Read-Time Clock Read / Write (RIC) 2.9 R/G/ Red / Green / Blue (Video) ROM 128Kx16, 200 nS
COMP. Monochrome Composite Video (Video) S RI Ring Indicate (RS232 Port) Amiga VIA, | MHz
CSYNC Composito Sync (Video) 24S. ROMEN ROM Enable (ROM) OKI Bus RIC
PETS: Clear to Sond (RS232 Port ) 6 RTS Request to Send 2 BiMGS Op-Amp
{D115:01 Processor Data Bus (68000) 12e3e6e709 RST Processor Reset 4 BiMOS Op-Amp
}OIR | Stop Direction (Floppy) 6.7 RXD Receive Dota (R5232 Port) 4 EIA Line Driver
LDKRD Disk Roed Dato (Floppy) 4,7 RW _[ Processor Reed/Write (68000) £2547 EIA Line Receiver
LDKWD {Disk Weite Data (Floppy) 4.7 LSEL Select (Par Timer
LOKWE [Disk Write Enable (Floppy) 4,7 SEL[ 330) Drive Select (Floppy) 4.6.7 DRAM 256Kx
LDMA Chip DMA Request Line (Chips) 2.4 SIDE Side Select (Floppy) 6,7 ORAM 2S56Kx1, 150 nS
LDRAL 8:0) ORAM Address Bus (DRAM) Zz i) TEP te n/ mmond (Floppy) 6.7 TTL 28.63636 MHz NTSC
ROl15:0] | ORAM Doto Bus (ORAM) 2.3,4,5,9 TRKO Track Zeno Sense (Floppy)... 6.7 TTL 28.37512 MHz PAL
| DTACK ae ca aa ERNEST 223.7 whe ere 000 Video Hubrid
nsf now { ) VM. emory
LDTR ote Terminal Reedy (RS232 Port} 6 VPA Valid Periphere] Address (68000) _|2.7
ia ripheral Fneble Clock (68000) [2.6.7 Verti (Video) 12.5.6
LEXRAM xpension Memory Present 223.9 WE Weite Eneble (DRAM) 2.349
FC(2:0) Function Code (68000) 251 WPROT Write Protect Sense (Floppy) 6.7
FIREQ/) Fire Button O/1] (Jousticks) 2.5.6 XCLK External Genlock Clock (Video) 2.5
HLT Processor Holt (68000) Zell XCLKEN External Clock Enable (Video)
YNC Horizontal Sync (Video) 22506 r
AES i x Pulse Lf Lonny | ——____1 6s} —____
Hoeeees eee R wees Sethe toe ATTEMPT TO FORCE NODE NUMBERS VIA SEQUENCE
Interrupt Priority Level] (68000) _ 12.4.7 vec a1 +5X 6
Keyboord Clock ({Keyboord) § RA
Keyboord Dato (Keyboord) 6 3 ~ euoe~ xr
Keyboord Reset (Keyboard) 6
pee Z lower Doto Strobes (68000) 12,7
r On LED 7 Audio Filter Disable 14.6 a
Schematic #312511-02, Rev. 5 A500 SERVICE MANUAL
Sheet 2 of 9
Note: R103-104,106-108,C101 ore for EMI Control eres
ond may be loaded with funny things... SAC 3214
JP2 controls where expension rem maps to:
A23 -> COQO000 (defeult), ALS -> 080900
R1Q9/C109,R10S5 Deteils, see ECO 880283
C101 FCC Filter Capecitor per ECO 870207
O(15:0)
<SDROI1S:0)
_ FLOPPY FUNCTIONS: 470x7 MO 4.7Kxg We
“Gee CONTROL FUNCTIONS RP104 rig RP1O1 Sg,
CLOEL *] * a
co aave-22 = <_OVR
a a U 5 op BOVE
ox Ns sha R01 <OXRDY
“L100 Nese!
= Ne——sst22 o719 _noneN —4> _ROMEN
ian = “evn 22 <_EXRAM
; R102 ‘les GA R Y _£LnRO ——>_CLKRD
mashe x) /—2-4 os _cunwep-22 43> _CLKWR
mia] [tetas os
2 RTET faa hs Fo4
aisle 19 —— 5 TA pp a GS asd s 22-,— 1
ae ay, | #8 Steer Dg eee aI _CCKO
—— — ay ir pg ae ve
ais[a3s 04 Patt sen,
aisle BS) Ge eos eee 3
_IPL(2:0) sass omen 538 ae
ait J oe
F: aioe te q ales De
many U10 3
_FC(2:0) mis : 4
See Note Abovel na Pome —¥4 ety
na d
et ch oa patent —Y Pe 5S _coac
"7M 15 eux ‘| Hiss 0, 2200 del rio7[ R108{" nies”
boat t—7 sol #825 885
R109 |- a mig BBs GTS 100pF]J 00pF]] OOpF],,
74LS: Rien UJ 2 = = =
aia oe RP 104] Peeia2 | : % oelis + vt sm SO -CASL
y+—_—___—_—_18 ° Mite ¥ Kelas ~tasupSs 47> _CASU
Tera oislsa_ os Z Ose Nas -ansop$? > _RASO
470x7|4.7Kx9 | aise : pat Ke sa"t? pea
013|s6_13 : Cm Kt—_—_*5 RAS1
VMA<>he2 van 9012/5712 . Bi Nhe eb2t > WE
- 011/580 N——# a ie
_VPAL>2 sie “tekeo— 3 = ©8371(PAL )
_DTACK<=2— we ores sf anne aN
ASS 1] a ik Oslset TT FAT AGNUS CN
oie US tala
; oles ones
R_W So 7 - oi : 83) se
_UDS<? _q-v0s cals 0. Ne prois nnol—2N
ps<2 8 tos Nain
-LDS> Neato 2 (> ORAB8:0)
sro
oe RST vec Kit ——“oro0
ie vr duns 4.7Kx9 =a
-HLT<S? 4 TH Nap?
he
RPIOL Ne ——ehoeoe
eet
RGA( 821)
0S
Ea le 22-
dias aha tires a3 26> 7MHz
18d peser been? Be) FIREL
aasyncp$t SsB<S _HSYNC
evsuc 78 SBS _VSYNC
; atsyncp82 ——5(>_CSYNC
ona A<TOMAL
smu ———4>_INT3
CLKENC>® Eq xcunen
RP103 L
XCLKC§* oe 22 NAY Ay — 38hrciK test
Schematic #312511-02, Rev. 5 A500 SERVICE MANUAL
Sheet 3 of 9
DRD( 15:0) ie
nu
as
eee ERE EERE
ciiiii
FERRETS
AS
AA7SG-15 UI2SE-15 Xx756-15
as U2G aa U.
a
#6
DRA( 8:0 )C>
TAF 244
RP202«r,,9368
RP 2020-4768
RP20267,4s68
RP2O 12-4168
RP20 lap 4368
RP20 ler ,qs68
RP20227, 4168
RP2O01e- 4768
RP 20 310-4968
lel mh & & & Eb
_EXRAM<F
RP20377¢,,868
_CASL 8 RP203sF ,as68
_CASU : S RP2033-, 9468
RASoL>*—_—§ 2
* JP3 rp203i¢, 9268 |
Note: JP3 swaps internel vs. expansion rem
2
3
CCK 5 (sa
5 (ahs
bis aah
_CLKROCO2 —eH U6
_CLKWRE* sp
V0 “he HN62402
a?
Note: $18072"0f**tgshibe Gory" 3 ahs 120K x 16 ROM
r info.
_OTACK ee . s12v | : he
(AZ
: a
i
-12v
a
_ROMENI
AC23:1)
0(1S:0)<
Schematic #312511-02, Rev. 5
A500 SERVICE MANUAL
Sheet 4 of 9
331
AUDINE>
RIGHT .22uF C335 CN3
+ TOK SE ENI303 ‘tet ween
moro
2 I
0331 9)"MPFi02
AOI oP LER SS ae
R336
F7eK V a suoi0
AUDOUT
EM1306 LEFT
+22uF C325 CN4
t EM1302 Tren snen |
I
_LEDL>
1488 0301 a ware
nate
Note: LED off, Filters bypessed i =
TAV =
_INT6
INT3
LINT2
—IPL(2:0)<¥
LRxD 10k 74838
- TxD RPSO1 p+ (>_MTRX
PAULA _KBRESETOS gee ery
8 3 6 4 _MTRC*
-SELOD> 74838
nKRD pb (>_OKWOB
. 74$38
DRD( 1510) bru 28 — pu (>_DKWEB
ORWE) 7
(RORG
RGA 8:1)
OMAL<¥
CCKC>
CCKQC>
RST
Note: Ground interconnection
roxp2 POTOX
Povp_—_ S<IP OTOY
3S
vu <P 0T 1X
py | POTIY
C31i} C3124 C313" C314
+047uF
_]-047uF _].047UF _[.047uF
neor audio “Jocks.
Schematic #312511-02, Rev. 5
Sheet 5 of 9
CCK
RIGHT JOY
DBSP
A500 SERVICE MANUAL
{>_FIFEC
<POTLY
puenia2? __4<IPQT 1X
Fie ce
EM1434
DRD(15:0)< DENISE
(ten XCLK
(te 74HC245 . Aya a _XCLKENCE
48 Ins ani
ens 8 a eats = fe
V5 leona mn Re Bett B i on
AB}
RGA( 8:11 U40
G3) G3
02] G2
ay & VIDEO
CCK >t —___—¥4ecx HYBRID
4 p HSYNC <#h
7MH2->2—____S}n w bs a
_CDACC>*@ 4. cane tak _VSYNC<>28
JOLANK BURST
PIXELSH
18lesync sync|22
conp}t®.
_CSYNCI>%
ycc
EMI 406
Eh opr +VXX
R406
d, a7 R : Note: Conponents designated os EMIxxx may be loaded
wP2uF caoz with EMI fliters, ferrite beeds or resistors!
C4
Notet Pin 2 and 21 of HYIl connected internally sor!
.-
RCA JACK
Note: R499 Controls Composite output
level for 390229-O1 Hybrid.
Schematic #312511-02, Rev. 5
Sheet 6 of 9
0(15:0)<&
AC 23:1)
10Kx9
RPSOL
_INT2<
_VSYNCE>#*
1OKxS vee
RPSOL'S,
_VMAC>
8520
CLAESET
U8
8520
RESET
' vec
RPSOL ng
_KBDATA
U7? fo €_KBCLocK
Jp
1 <_FIRE1
A500 SERVICE MANUAL
KEYBOARD CONNECTOR
LEO“ N3906
O-Piu BIL
CK
—KBRESETQ)
<_FIRES _MTRO>
<_RDY
[|
:
~<a
my _TRKO
=
[|
|
<_HPROT
<o_CHNG
{>_LED 10Kx3 4 CN13
Cove rpsoi's) CN7
0625S
ver
perf = ry]
a INIT 4 ENtS20
Pes [ au <_IORESET
i ||
i Ez RS232 DECOUPLING
PPD(7:0) a)
10Kx9 vec |
RPSOL ; =
TO8eF = i
1000 PARALLEL PORT
100pF F -etts23
100pF EMIS24
spe |
ili 1OKx9 vec
RPsal's'
pcp-'8 iF! = =
sp <_ INDEX ,
1 HE
rns
oe a A “10D
a
nt _RxO0<F
er aaa ie 72oF | L—4> aud IN
a csel
pole
s€N1562
gENISO3
pont ([>_MTR +22uF 1), AUDOUT
ras'$ > _SEL3 A
_SEL2
SELL
_SELO
SIDE
DIR
STEP ae
Note: EMISQ1-S03 ere loaded with 47 Ohm 1/2 W resistors
Schematic #312511-02, Rev. 5
17 SIDE
£7 >_WPROT
£1 >_TRKO
4.2) DKWEB
4.1) DKWDB
B21) STEP
BI ADIR
§&<]_SEL3
eI SELI
S.4>_ INDEX
Sheet 7 of 9
—RDYS
_OKRD<)
_MTRXC>4 To0eF
.SEL2C* To0ae
_IORESETIO&2 ea
_CHNG<F 2
EXTERNAL FLOPPY
wee
R711 a ma ne writ
" w Li, RST
Zhe U 42), Af
NESSS
Sl yResH
-| | Torscw
e711 C712 ]4 sl.
“ad wtek “leuk nor lie
of cote
+22uF
INTERNAL FLOPPY
Gia
_CHNG<F
aI NDEX< #4
_SELOL>4®
_SELIC™
_MTROL>4
DIRC>*2
STEPS
_OKWOBL>“2
_DKWEBL>“+
_TRKO<#7
_WPROT <P
_DKRO<#42
SIDEC =
_RDY<P2
_KBRESET
Ewe) ie) LON
74LS32
A500 SERVICE MANUAL
EXPANSION
mel
3 2
wee
a
oar
83 40°] PT En} TERT TOR]
On ae CONFIG 412y
Py ae +4<_CCKO
cDACC is 16 2.8 CCK
—OVRP}—— 1718) + 24>XROY
-INT2<O#& 9 26°
2, 22% ABS _INTS
=< °29 FP
[-——~}*25 “e®
== ®7 Ys? _FC(2:0)
ae
10 oT?
2. 36 33
: — —_
a :
16
i"
Al2321)<& 36.
z es ee 23> _DTACK
a 67 68 248<SR_W
ss 53 10% 2<>_LDS
. ©, 12° 2<>_UDS
10 13 1? 2<>_AS
aa oe 7s 76°
—=—=—=-~
——— "79 88°
‘ }—*a1 87°
: a3 aa
"as 86"
DL 15:01<
_1ORESET
coum i,
= U37
"(> _RESET
in
i
Schematic #312511-02, Rev. 5 A500 SERVICE MANUAL
Sheet 8 of 9
POWER INPUT
LINE FILTER
CN8 _ Bre FLOPPY POWER
vec
4-PIN STL
+12v
- UN I2
COIL + C812}, CB13|4 cBl4 |, CBS 4
“| 190uF “| 47uF Parr “| 47uF Prue
Note: Wl and W2 are ground plane
NOTE: HEAVY LINES INDICATE A $V continuity jumpers. (FCC)
SINGLE POINT CONNECTION
ot Hee
weu
! 74F04
2
U33
entioi 7
fe
74F04
ail L u33
“EE
DECQUPLING
5-8
Schematic #312511-02, Rev. 5 A500 SERVICE MANUAL
Sheet 9 of 9
XDRD(15:0)
XDRAB( 8:0)
REEEOEORBRERDRI
Xx256-1
U
bes SZRZERES
Real Time Power
RP9013-,4.68
RP9019-— 5168
TT rP902i75268
RP9O02s~ 4668
RP9027-, 4868
|_— (aes
ic
el aa
i Real Time Clock
i RP903i-,9268 ~
|_| RP90337 3468 z
hw Lufos Ug R12 TP3
$$ $< g S
RP9O3sr 9668 a sto.elt
| | RP9O327 068 MSM62428
Az
———— |
02+
28x
aut 6.8-45pF cg] 2
lod wo C912
X0(1530) od we
Liss:
q.cso
XA( 2331) =
—XCLKRD
_XCLKWR
a] 5
cs3
22uF]_ =
-|,c902 -/,c903
t 47uF > 47uF
a i oa [a =] 3]
cs8 =P css t c60 ? cer cea] c63 "|
[vs0] uss U6O U61 ar
220] <1 . . 220]
L1G)
ry
8
e
Li
16
v
8
e
114
16]
Ry
8
e
LL
A
in
8
5
4
Schematic #312511-03, Rev. 6A/7
A500 SERVICE MANUAL
Sheet 1 of 8
Jumpers and Stuff Connectors
DESCRIPTION REF TYPE }DESCRIPTION [PAGE
|
Keyuboerd Reset CN1 OBSP [Mouse/Joustick |
Memory Addr. CO vs 08 CN2 DB9P Mouse/ Joust ick 2 s—
Exponsion RAS Select {CN3 RCA-J Right Audio Output
NTSC/PAL Selection CN4 RCA-J_ |Left Audio Output
Genlock Clock Select CNS 0B23S_ [Externol Floppe
TMHz Clock Option CN 0 P_IRS232 Seriel Port
Expension/Tick 0 CN7 OB25S_ |Perellel Printer Port |6
ICN6 [SQ DIN |Pouer Supply Connectors
CN9 DB23P_ |Video Output 5
CN10 RCA-J Gonposite Video S
nterno lo
Internel Floppy Power
CN13 Keuboord Connector 6 ECO Log
b ECO NUMBER | DESCRIPTION
i a 03703768
_ Hen ENS IS Ee Sl
aS ee
Signal Glossary
SIGNA DESCRIPTION (AREA) PAGES SIGNA DESCRIPTION (AREA) PAGES
| 2BMHZ [28.63636 MHz Moster Clock 12 PEeEN [Light Pen Trigger
(1). ) et
AL23: Processor Address Bus (68000) 223.7 MTRO Motor Qn - Drive 0 (Floppy)
ri) i -aea MOV/MOH Mouse 0 Quedrature V/H (Joysticks)
a Address Strobe (68000) Ve) MIV/MJH Mouse Quedreture V/H (Joysticks)
A N d oput (RS232 Port) 4,6 LOVE | Overloy ROM over RAM
AUDOUT Audio Qui ous (RS232 Jock] 4.6 Ove : Override System Decoding
BEER | Bus Error (6800 * XELS Genlock Pixel Switch (Video)
ni(68000) ze] POTOX/O Pot Linas 0 : Key Components
LBGACK | Bus Grant Ackn 2 7 POTIX/1Y i
BLISS Blitter S]owdown (Chips) 2 POUT Peper Out (Perellel Port) REF CHIP |DESCRIPTION PAGE
ee ee eee 12.7 LPPD{ 7:0) Parallel Port Date (Parallel Port}
R s Request (68000) Zs RAMEN RAM Eneble (Chips) 68000 Processor
BUSY vy usy (Perellel Port) 6 REGEN Chip Register Enable (Chips) Fot Agnus - NTSC
ASL/U Column Address Strobe (DRAM) 253 RASO/ Row Address Strobe (DRAM) Fot Agnus - PAL lt
K/CCK Color Clock / Quodreture (Chips) 224.7 LRDY Drive Reody (Floppy) 7 Agnus HR It
AC MHz Quadroture Clock (Chips) 1 RESET [General Reset 1 Poula
HNG Media Change (Floppy) Z 3 i Bus (Chips) 12.4 Denise
CLKRD/WR ed-Time Clock Read / Write (RIC) 9g R/G/B Red / Green / Blue (Video) 5 Denise HR t
che | Monochrome Composite Video (Video) Ring Indicate (RS232 Port) 16 Gor 4
LCSYNC Composite Sync (Video) +225 ROMEN ROM Eneble (ROM) 12,3 ROM 128Kx16, 200 nS
CTS Clear to Send (RS232 Port} 6 RTS Request to Send (RS232 Port) 6 Amiga VIA, | MHz I
2:0) Processor Dato Bus (68000) 2232657 RST Processor Reset ( ) 2.4
DIR Step Direction (Floppy) 16,7 RXD Receive Doto (RS232 Port) 4,6 U14 BiMGS Op-Amp
KRD Read Data (Floppy) 47 [RW Processor Read/Write (68000) 12.6.7 BiMOS Op-Amp
Floppy) 4.7 SEL (Porallel Port) 16 U38 EIA Line Driver
DKWE QNisk Write Enoble (Floppy) 4,7 SEL[ 3:0) Drive Select (Floppy) 4,6 U39 EIA Line Receiver
Coma Chip DMA Requost Line (Chips) Select (Floppy) 16.7 42 Tiner
LDRAL BI LDRAM Address Bus (DRAM) 3 STEP: Step In/Out Commend (Floppy) | 6,7 U16-19 Josst ORAM _IMxl, 150 nS
IR 5:0] QRAM Date Rus (ORAM) 243,4,5 TRKO Track c nse (Flo } 6.7 U20-23 lesst ORAM IMx1, 150 nS
Dato Sot Ready (RS232 Port) 6 TxD Tronsmit Doto (RS232 Port) 4,6 XI TTL 28.63636 MHz NT
TACK Data Transfer Acknowledge (68000) VaR a) VMA Volid Memory Address (68000) 2.6 OSC TTL 28.37512 MHz PA alt
LDIR Dota —Terninoal Ready (RS232 Port) 6 VPA Valid Peripheral 1
| Peripheral Enable Clock (680900) 12.6.7 VSYNC Verticol Sync (V HY 1 osst Video Hubrid 5
HEXTICK Fxponsion Praesent / RTC Tick 2.3 WE Write Eneble (DRAM) 3
Function Code (68900) [2.7 WPROT rite Protect Sense (Floppy) G27
FIREQ/] Fire Button O/1 (Jousticks) 225.6 XCLK Externe] Genlock Clock (Video) 12,5
HLT Processor Halt (68000) [2.7 XCLKEN xterne] Clock Enable (Video) 12.5 _
HSYNC Horizonte] Sync (Video) 2.5.6 XRDY Externol Doto Reody 12.5
INDEX Index Pulse (Floppy) 6,7
c ) 4,6.7
i : P 1_ (68000) 2 f 7
Nterrupt Prior vy)
eI, tority Les rE] oe ATTEMPT TO FORCE NODE NUMBERS VIA SEQUENCE
Keyboard Date (Keyboerd) 6 vec ~12V6 +5X 6
Keyboard Reset (Keyboard) 6 == yA Ke web ale a hee
Upper / Lower Dato Strobes (68000) 257 : Oe
Power On LEO / Audio Filter Disable 4.6
FI/RIGHT |Left Right Audio (Audio) 4
5-10
Schematic #312511-03, Rev. 6A/7
A500 SERVICE MANUAL
Sheet 2 of 8
AC2331)
Notet Various components ere for EMI Control 1]
and moy be losded with funny things... Belo 1550)
JP2 controls where expansion ram mops tot A> DRO 1529)
A23 -> COOD0B (defoult), AIS -> 080000 ‘Gen FLOPEY FUNCTIONS. 470x7 J 4.7Kx9
XR1 is odded to some boerds per ECO 880283 fie agrees, ee: FERRELL ONS RP104 RP101
vec | sd aren U 5 . | - ;
470x7 4.7Kx9 _ tinandp 2 >_EXTICK
| ieee = cael
ea) 1 gl | “ on}! OVE
: et = Ne 5719 Ei
+ = ova <J_OVR
RP104| | |RP102 MC68000 7 erences
t—v GARY no <OXRDY
Cc {ie io
ee || Pn R14
=i 4 RONEN fr (>_ROMEN
_BGACKC> 1 i
BEERS ° 8 OTE tun C>_CLKRD
eel de Las, ACL MHR} (>_CLKWR
my a
iy qos § §
-IPL(2:0)> | 4 4
(aes somes moe
re ean ate
~FC( 2:0) a) > _CDAC
See Note Above! 74F04 Rpio3
xR1 Pot — has >CDAC
ES “7 47pF | U33 39
TMHzC> E106
9 ui 24FO4 RPio3
iy : ot hy >_ccKa
mw Ugs
U2 fF
= — J4FO4 e103
° {>_CCK
_VMAS a ver J Sees Hl
ona7}s9_2. U3 3) £94
_VPAC> mt tN Pies 45> _CCK_A
_DTACKC> le £106 re
ASS KN ~ 66 CK.
N 7
Hoe Agnus HR i [> DRA(8:0)
-UDSS are
LDS toute
pi—3N
RSTS patN
-HLTS
(>RGA( 831)
ps (>_CASL
b (>_casu
bs (>_RASO
has ypSs [>_RAS1
sept (>_WE
See or 5>7MHz_A
a7 (>7MHz
-LPenbp?® S<| LPEN
aromncp et ——Ssic>_HSYNC
ysyncp22 B<>_VSYNC
terncp® (>_CSYNC
<OOMAL
- ——>_INT3
6} “coarser, SPARE
= RP1034— oy
Note: PAL uses 28.37516 MHz ss sana 39
5-11
Schematic #312511-03, Rev. 6A/7 A500 SERVICE MANUAL
Sheet 3 of 8
one 1
Note: RPIQS-RP111 are optionel internel bus
termination, and ore not normally loeded.
CeeeeReceCueeel
CG GCEGEREEEEEE
SEES ERIS EET
[|
|
a
a
||
[|
|
|
||
|
|
H
DRA( 8:0) ice a nay
[| 1
aa I
Hea
——H
| | |
JP7A S—F
= | |
_EXTICK<P+S aul a
os Al |
_CASLC> SiiAl | | 6
_RASOL> 182A3 2y RP203 3 4 68
ree .
WEL 142R4 2y o * 2, =
eo aly? | Notes: JP3 swaps internel vs. expansion ran
Wage wiygls A woroy_sytep—2t
ss 8 ——
= y,
_CCK_AD a
ee Cmennl RK 0 M
ane eae
_cLKRoo>2-——_— aa
_CLKWRE>2@—____— [| _ROMENC>
ApDKxax T 4 TKx 9x f
RP108 RP110° Al23:1
5 al 5 +12¥ |
= = D(15:0)<<>
0615:0)<c#t av
~JKx9x J 4e7Kx9x"f 4.7Kx9x SPARE
4 gx :
sii |RP1063 il
AC 2321) Cte _2
x
RP201 ip,qz 68
Nh
ip
S,
hi
Ri]
we
yh
5-12
Schematic #312511-03, Rev. 6A/7
Sheet 4 of 8
—IPL(2:0)<#
ORD(1S:0)<>
RGA( 8:1 >
OMAL<¥
CCKC>
CCKQC>
—RST&>
JPIOR gang
AUDINCO* tit
0332
RIGHT ky [Fo] ‘ass 800pF
[27°F
c321
vluF
R321
c322
£306
LEFT 1176]
270pF
Note: LED off, Filters bypossed i
+Av
+AV
83077
1488 “ 1
R306
LEDC 4 aK 2N3906
Uu38 0301 >
tox +OluF
R308" 308
~AV +
aare
15 INTE <_INTS6
(4 -tntap2 <1_INT3
¥ -tNT2D <_INT2
4 yee ep
i—s “Pe S<_RxD 10K
a ——a] a = 74LS38
yr ss} P nl TxD
1x0) C_ RPSO1 jl U 5 FG,
Y ntexP
pt _KBRESETCOS df noneser Leap
TRON!
— “ MTROS rdan GARY
a - ;
i R305 ~SELOL> ds 54 1 g
——"| th HY 741838
p= <_DKROD oe] 741838
Dxwop ono :
A—} me FLOPPY cD,
—o — FUNCTIONS, _
21
—
V fi es ee pth
ee ‘<Porey
Ct GOH BEF! <POTIX
<POTIY
c3ii-) c3i2z~ cai3%| C3l4
-047uF ].047uF ].047UF | .047uF
|
Fase2|*| mae
Note: Ground interconnection neer audio “Jocks.
MPF 162
AUDIO FILTERS wa are
6800pF
(>_MTRX
T>_MTRO
{>_OKWOB
{>_DKWEB
A500 SERVICE MANUAL
AUDOUT
LEFS
CN4
Tren aacn , 1
+13
Schematic #312511-03, Rev. 6A/7 A500 SERVICE MAN
Sheet 5 of 8
vee LEFT JOY ue
4.7Kx9 + CN1 oA eT
RP401 DBSP BAO
41}i p
2 4 Erg E415 aoe
E401 tr “EAP IRER
[cara ge err a reg
74L$157 apt ; E416
ccK_Bt> 1 i ae EAN ee 70eF rer
>: Je U1is'§ Ht Sk pores APOTGL
47pF £441 1 4 2ALs. “|1000pF7|1000 rhe
: T0oF p jpF~}1 OO0pF
E109. £443 A 2 2al5.
4 70eF ev care] c4i3J cau
£444 1 3 in
= ‘470eF BY oa
442 EF se ey Bp RIGHT JOY vec
15 any CN2 I ge5
36 = G faht | DBOP R408,
; 8
= BAZ 1 sence 4
alg arr i pee —4A>_FIRE1
3 Soir
= i
RP4O5 ~ Ee se006F a ic AP OT LY
\ EAP mig AIPOT IX
= “|1000pF|1000pF |1000pF
= C422 J C423.) C421
Note: RP40S5 Not Used
Go ta 1
DENISE HR
ORD(15:0)<
RGR
on aalt2
(RORG
pane 74HC2 45 roy?
= —— Heo HY I XCLK
eons mi i482 err —XCLKEN<P PIXLSW
RGA(B:1) U40 _CCK_C
sah oR Bag rt
102
CCK ken othe SREB BSE we VIDEO RPAOZ ar pyjs 47
Ala au 0 HYBRID RP4025¢ 6 47
_cont aancaas d esas
03)
7MHz_A oat 2 alps 4
BI 16 15)py
po HSYNC <2. RP 403 sr ,J6 47 P 1SOpF Hsync
“VSYNCS 5 RP40377, 98 47 VSYNC
ixesy Toe :
_CSYNCC>*—————rann i —!8lestic srwc
aurstp-!8 _,
‘CONP}
VID =
| tsar HY1A
COLOR
teare ANNEX
Te eee Noter R409 Controls Composite output
level for 390229-01 Hybrid.
RP403 Elayyne! 47 3s> CCK_C
RP4O2 if qe 47 SS>P1XLSW
RP403 of aio 47 _ J
Ia
Tm -OluF
+VID 12V
R406 ae rsos | ({F
7 Vac
4.7 a] A 4.7
J 7 | s Note: Components designeted es Exxx may be loeded
-22uF = C402 _] + A © 10401, |- i
uso] = hve, with EM] fliters, ferrite beads or resistors!
ca >
-| =| -| (oe .
3300uF & 3300uF
Notet Pin 2 end 21 of HYl connected internally a
Schematic #312511-03, Rev. 6A/7 A500 SERVICE MANUAL
Sheet 6 of 8
RPSOl__“f
ik
DI15:0)<> ss
5 <_KBDATA
U7 Te] <_KBCLOCK KEYBOARD CONNECTOR
ie? 5
Naseer)
Sieeereeerer)
he sep JP8 arin fib
A231 1 ae “spas 5 _KBCLOCK cK
—ae Ge [>_LPEN _KBDATA<
_KBRESET<#
she, BOLO "FP
7 Sas? GROUND
RSO STATUS)
INUSE
{usr es CN13
RPSO1 d
{10K .
_INT2<fe2— ‘i <_IORESET
_VSYNCC>2 + |
_EXTICKC2-y: (en
P78 re eae RS232 DECOUPLING
PPD(7:0)
spe
U8 Jo | |
28h, RPSOI YS
4
RPSO1 “4
‘10K
3! F ne AUDIN
_VMAC> dup
R_WO>*2
Ee AAUDOUT
_INT6<oR
_HSYNCD>#
_RESETCO2
Note: E501-503 ere looded with 47 Ohm 1/2 W resistors
Schematic #312511-03, Rev. 6A/7 A500 SERVICE MANUAI.
Sheet 7 of 8
EXPANSION Pl me > re
PIA PIB -DKRDS : > WPROT
[>_TRKO
<_DKWEB
<_DKWOB
JP6 |_STEP
1 2
7MH20>%————_$a8 — _NTRXD 2” . mee
_SEL20>5 ae £2 SELL
; _CCKa —TORESETS r 3 B.>_ INDEX
i wie ica CCK _CHNGI ns
_OVR<# A>XRDY
_INT2<o468 z
48> _ INTE
- =xc3
47pF |. =
1 _FC(230)
EXTERNAL FLOPPY CN11
IPL(2:0) CN11 CNILB
_CHNG<CP2
—2<>_BEER _INDEX<B2
2< VPA _SELOL>“S
2aB<TE _SELI(>&2
28<> VMA
ze nes
2<>_HLT _STEPD®
A>_BR _OKWDBC>
A>_BGACK _DKWEBLO>M2
Al23:1)<> 2<7_BG _TRKO<2
2<>_DTACK _WPROT <P
248<SR_W _DKRO<+2
2<>_LDS _SIDED&2
2<>_uD0S _RDY<#
2<>_AS
“ INTERNAL FLOPPY
- _RESET
_10ORESET
DUIS:0)<
= vce
R715
_KBRESET
a i C711
-33uF LL
Schematic #312511-03, Rev. 6A/7
Sheet 8 of 8
POWER
CN8
INPUT
+12V
NOTEs HEAVY LINES
coor] ceo]
INDICATE A
SINGLE POINT CONNECTION
yec
cod, 8121+ ce13 dy ce14“|4 cost, C816 “|+
2B1UF [3 Pieour [our “| 106uF Froour [1900 “tour
at
Notes U2Q0-23 end C20-23 not loaded for 512K systen
VECOUPLING
A500 SERVICE MANUAL
a ioe ca Med ON a
vec
4-PIN SIL
= CN
Notes Some drives are +5 only...
oFHREs
+VCB
T4FO4
2
U33
GROUNDED HOLES; &c.
MT1
MT2
MT4
MTS
MT6
MT7
Schematic #312605-01, Rev. 6C
Sheet 1 of 1
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+12X
A500 SERVICE MANUAL
Notes: Some configurations of this RAM expansion
require mods to rev 3 end 5 ASOD boerds
end/or use of the Agnus HR 2MB bond-out.
U1-U4 are generic 256K-bit x 4
RP911,RP912 ere optionel DRD Termination
A8B/RAS Setup Time Control
TPS is Clock Calender Frequency Test Point
C10
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A500 SERVICE MANUAL
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A500 SERVICE MANUAL
Input/Output Connectors
This section lists pin assignments for several input/output connectors on the
Amiga. The information in this section is highly technical and is intended only
for those expert in connecting external devices to computers. You do not need
this information if you use a cable specifically designed for use with the Amiga
and the add-on you want to connect.
For information about connectors not described in this section, see the Amiga
Hardware Manual.
If you attach peripherals with cables other than those designed for use with the
Amiga, note: some pins on Amiga connectors provide power outputs and
non-standard signals. Attempting to use cables not wired specifically for the
Amiga may cause damage to the Amiga or to the equipment you connect.
The descriptions below include specific warnings for each connector. For more
information about connecting add-ons, consult your Amiga dealer.
In the descriptions that follow, an asterisk (*) at the end of a signal name
indicates a signal that is active low.
5-19
A500 SERVICE MANUAL
Serial Connector
In the following table, the second column from the left gives the Amiga pin
assignments. The third and fourth columns from the left give pin assignments for
other commonly used connections; the information in these two columns is given
for comparison only.
IPPIIIDIVIIIOG
, 4 , 4 4 0 0 ya , Mt a 0 v4
WARNING: Pins 9 and 10 on the Amiga serial connector are used for
external power. Connect these pins ONLY if power from them is required
by the external device. The table lists the power provided by each of these pins.
Amiga
Pin 500 RS232 HAYES® Description
l GND GND GND FRAME GROUND
Zz TXD TXD TXD TRANSMIT DATA
3 RXD RXD RXD RECEIVE DATA
4 RTS RTS REQUEST TO SEND
5 CTS CTS CTS CLEAR TO SEND
6 DSR DSR DSR DATA SET READY
7 GND GND GND SYSTEM GROUND
8 DCD DCD DCD CARRIER DETECT
9 +12V +12 VOLT CARRIER
10 -12V — 12 VOLT CARRIER
11 AUDO AUDIO OUT OF AMIGA
12 S.SD SI SPEED INDICATE
13 S:CTS
14 S.TXD
15 TXC
16 S.RXD
17 RXC
18 AUDI AUDIO INTO AMIGA
19 S.RTS
20 DTR DTR DTR DATA TERMINAL READY
21 SQD
22 RI RI RI RING INDICATOR
23 SS
24 TXCl
A500 Parallel Connector
A500 SERVICE MANUAL
WARNING: Pin 14 on the Amiga parallel connector supplies +5 volts of
power. Connect this pin ONLY if the power from it is required by the
external device. NEVER connect this pin to an output of an external device
or to a signal ground. Pins 17-25 are for grounding signals. DO NOT
connect these pins directly to a shield ground.
Pin
l
NO
Name
STROBE*
DO
Di
D2
D3
D4
D5
D6
D7
ACK*
BUSY
POUT
SEL
+5V PULLUP
NC
RESET*
GND
GND
GND
GND
GND
GND
GND
GND
GND
Description
STROBE
DATA BIT 0
(Least sign. bit)
DATA BIT 1
DATA BIT 2
DATA BIT 3
DATA BIT 4
DATA BIT 5
DATA BIT 6
DATA BIT 7
ACKNOWLEDGE
BUSY
PAPER OUT
SELECT
+5 VOLTS POWER (100 mA)
NO CONNECTION
RESET
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
SIGNAL GROUND
RGB Monitor Connector
-
PIDPIDIDIGDIGG
IPIPIIIIPIO
A500 SERVICE MANUAL
WARNING: Pins 21, 22, and 23 on the RGB monitor connector are used for
external power. Connect these pins ONLY if power from them is required
by the external device. The table lists the power provided by each of these pins.
Pin
OoONNNBR WN
— mt (OO
—_- ©
pee eee tt
OmeArARKANA WN
N
So
Nn NY
wn
Name
XCLK*
XCLKEN*
RED
GREEN
BLUE
DI
DB
DG
DR
CSYNC*
HSYNC*
VSYNC*
GNDRTN
ZD*
Cit
GND
GND
GND
GND
GND
-12V
+12V
+5V
Description
EXTERNAL CLOCK
EXTERNAL CLOCK ENABLE
ANALOG RED
ANALOG GREEN
ANALOG BLUE
DIGITAL INTENSITY
DIGITAL BLUE
DIGITAL GREEN
DIGITAL RED
COMPOSITE SYNC
HORIZONTAL SYNC
VERTICAL SYNC
RETURN FOR XCLKEN*
ZERO DETECT
CLOCK OUT
GROUND
GROUND
GROUND
GROUND
GROUND
— 12 VOLTS POWER (50 mA)
+12 VOLTS POWER (100 mA)
+5 VOLTS POWER (100 mA)
8.22
=
A500 SERVICE MANUAL
Mouse/Game Controller Connectors
There are connectors labeled ‘‘JOY1’’ and “‘JOY2”’ on the back of the Amiga 500.
If you use a mouse to control the Workbench, you must attach it to connector
JOY 1. You can attach joystick controllers to either of the connectors. To use a
light pen, you must attach it to connector 1. The following tables describe
mouse, game controller, and light pen connections.
WARNING: Pin 7 on each of these connectors supplies +5 volts of power.
Connect this pin ONLY if power from it is required by the external device.
Connectors 1 and 2: Mouse Connections
Pin Name Description
| MOUSE V MOUSE VERTICAL
2 MOUSE H MOUSE HORIZONTAL
3 MOUSE VQ VERTICAL QUADRATURE
4 MOUSE HQ HORIZONTAL QUADRATURE
5 MOUSE BUTTON 2 MOUSE BUTTON 2
6 MOUSE BUTTON 1 MOUSE BUTTON 1
Ki +5V +5 VOLTS POWER (100 mA)
8 GND GROUND
9 MOUSE BUTTON 3 MOUSE BUTTON 3
A500 SERVICE MANUAL
Connectors 1 and 2: Game Controller
Pin Name Description
| FORWARD* CONTROLLER FORWARD
2 BACK* CONTROLLER BACK
2 EERE CONTROLLER LEFT
4 RIGHT* CONTROLLER RIGHT
5 POT X HORIZONTAL POTENTIOMETER
6 FIRE* CONTROLLER FIRE
Z +5V +5 VOLTS POWER (100 mA)
8 GND GROUND
9 POT Y VERTICAL POTENTIOMETER
Connector 2: Light Pen Connection
Pin Name Description
LIGHT PEN PRESS LIGHT PEN TOUCHED TO SCREEN
LIGHT PEN* CAPTURE BEAM POSITION
+5V +5 VOLTS POWER (100 mA)
GND GROUND
OOW~DARWHN
5-24
External Disk Connector
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Power Supply Connector
Pin
MA BR WN —
Name
/RDY
/DKRD
GND
/MTRXD
/SEL2B
/DRESB
/CHNG
eS
/SIDEB
/WPRO
/TKO
/DKWE
/DKWD
/STEPB
DIRB
/SEL3B
/SEL1B
/INDEX
+12
Name
+5Vdc @ 4.3A
SHIELD GROUND
+12Vdc @ 1.0A
SIGNAL GROUND
-—12Vde @ .1A
A500 SERVICE MANUAL
Description
Disk Ready—Active Low
Disk Ready Data—Active Low
Ground
Disk Motor Control—Active Low
Select Drive 2—Active Low
Disk RESET—Active Low
Disk has been Removed from Drive—
Latched Low
5 VDC Supply
Select Disk Side—O = Upper 1 = Lower
Disk is Write Protected—Active Low
Drive Head Position over Track O—Active
Low
Disk Write Enable—Active Low
Disk Write Data—Active Low
Step the Head—Pulse, First Low then High
Select Head Direction—0 = Inner | = Outer
Select Drive 3—Active Low
Select Drive 1—Active Low
Disk Index Pulse—Active Low
12 VDC Supply
A500 SERVICE MANUAL
86-Pin Connector
Pin Name Pin Name
1] gnd 44 IPL2*
2 gnd 45 Al6
3 gnd 46 BERR*
4 gnd 47 Al7
5 +5§ 48 VPA*
6 +5 49 gnd
7 exp 50 E
8 —12 51 VMA*
9 exp 52 Al8g
10 +12 53 RES*
11 exp 54 Al9
12 CONFIG* 55 HLT*
13 gnd 56 A20
14 C3 57 A22
15 CDAC 58 A2l
16 Cle 59 A23
17 OVR* 60 BR*
18 XRDY 61 gnd
19 INT2* 62 BGACK*
20 PALOPE* 63 PD15
21 A5 64 BG*
22 INT6* 65 PD14
23 A6 66 DTACK*
24 A4 67 PD13
25 gnd 68 PRW*
26 A3 69 PD12
27 A2 70 LDS*
28 A7 71 PD11
29 Al Te UDS*
30 A8 73 gnd
31 FCO 74 AS*
32 A9 75 PDO
33 FC] 76 PD10
34 Al0 77 PD1
35 FC2 78 PD9
36 All 79 PD2
37 gnd 80 PD8
38 Al2 8] PD3
39 Al3 82 PD7
40 IPLO* 83 PD4
41 Al4 84 PD6
42 IPL1* 85 gnd
43 AIS 86 PD5
C= Commodore
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1200 Wilson Drive
West Chester, PA 19380
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